
MOTOROLA
Index
Index-9
Q–R
options available, 6-10
protection violations, 6-14
PTEGs (PTE groups), 6-27
PTEs (page table entries), 6-27
Q
QACK signal, 8-45, 9-37, 9-40
QREQ signal, 8-46, 9-41
Qualified bus grant, 9-6
Qualified data bus grant, 9-22
Quiesce acknowledge signal, 10-4
Quiesce request signal, 10-4
Quiescent state, 10-4
R
R bit, 6-39
Read atomic operation, 4-20
Read operation, 4-20
Read with intent to modify operation, 4-20
read-with-intent-to-modify (RWITM), 4-8
Read-with-intent-to-modify (RWITM) EXAMPLES,
4-19
Real address (RA),
see
Physical address generation
Real addressing mode,
see
Direct address translation
Recognition, 5-2
Recoverable exception, 2-8
Reduced-pinout mode, 9-40
Referenced (R) bit, 6-11, 6-22
maintenance recording, 6-11, 6-21-6-24, 6-31
Registers
cache locking register summary, 4-32
cache locking registers
HID0, 4-33
HID2, 4-33
MSR, 4-33
configuration registers
MSR, 2-6
PVR, 2-4
exception handling registers
DAR, 2-8
DSISR, 2-9
SPRG0–SPRG3, 2-20, 5-11
SRR0, 2-9
SRR0/SRR1, 2-19
implementation-specific registers
DCMP/ICMP, 2-16
DMISS/IMISS, 2-16
HASH1/HASH2, 2-17
HID0/HID1, 2-10, 2-14
IABR, 2-21
RPA, 2-17
memory management registers
BAT, 2-8
SDR1, 2-8
SR, 2-8
supervisor-level
BAT, 2-8, 2-19
DAR, 2-8
DCMP/ICMP, 2-16, 6-34
DEC, 2-9
DMISS/IMISS, 2-16, 6-34
DSISR, 2-9
EAR, 2-9
HASH1/HASH2, 2-17, 6-35
HID0/HID1, 2-10, 2-14
IABR, 2-21
MSR, 2-6
PVR, 2-4
RPA, 2-17
SDR1, 2-8
SPRG0–SPRG3, 2-20, 5-11
SR, 2-8
SRR0, 2-9
SRR0/SRR1, 2-19
TB, 2-9
user-level
CR, 2-2
CTR, 2-4
FPR0–FPR31, 2-2
FPSCR, 2-2
GPR0–GPR31, 2-2
LR, 2-4
TB, 2-4
TGPR0–TGPR3, 6-33
XER, 2-4
Rename buffer, 7-2
Rename register operation, 7-15
Reservation station, 7-2
Reserved instruction class, 3-8
Reset
HRESET signal, 8-42
reset exception, 5-19
settings caused by hard reset, 5-20
SRESET signal, 8-43, 9-41
Reset configuration signals, 8-43
Reset signals, 8-42
Resource ID, 9-18
Retirement, definition, 7-2
RI, 5-14
RISC, 1-1
Rotate and shift instructions, 3-14, A-17
RPA (required physical address), 6-36
RSRV signal, 8-45, 8-46, 9-42
F
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