
6-12
G2 PowerPC Core Reference Manual
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MOTOROLA
MMU Features
Figure 6-5. General Flow of Address Translation
(Real Addressing Mode and Block)
6.1.6.2
Page Address Translation Selection
If address translation is enabled (real addressing mode not selected) and the effective
address information does not match with a BAT array entry, then the segment descriptor
must be located. Once the segment descriptor is located, the T bit in the segment descriptor
selects whether the translation is to a page or to a direct-store interface segment, as shown
in Figure 6-6. Note that the G2 core does not implement the direct-store interface, and
accesses to these segments cause a DSI exception. In addition, Figure 6-6 also shows the
way the no-execute protection is enforced; if the N bit in the segment descriptor is set and
the access is an instruction fetch, the access is faulted as described in Chapter 7, “Memory
Management,” in the
Programming Environments Manual
. Note that the figure shows the
flow for these cases as described by the OEA and, therefore, the TLB references are shown
as optional. Since the core implements TLBs, these branches are valid, and described in
more detail throughout this chapter.
Perform Address Translation
with Segment Descriptor
Access Faulted
Compare Address with
Instruction or Data BAT
Array (As Appropriate)
Translate Address
Perform Real
Addressing Mode
Translation
Effective Address
Generated
Continue Access
to Memory
Subsystem
Instruction
Translation Enabled
(MSR[IR] =1)
Data
Translation Enabled
(MSR[DR] = 1)
(see Figure 6-6)
Instruction
Translation Disabled
(MSR[IR] = 0)
Data
Translation Disabled
(MSR[DR] = 0)
BAT Array
Hit
I-Access
Access
Protected
Access
Permitted
Perform Real
Addressing Mode
Translation
(see the
Programming
Environments
Manual
)
BAT Array
Miss
D-Access
F
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.