
7-24
G2 PowerPC Core Reference Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Instruction Scheduling Guidelines
branch instruction performing the evaluation. Separation of the branch and
mtspr
instruction by more than nine instructions ensures the register values will be
immediately available for use by the branch instruction.
Schedule instructions such that they can dual dispatch.
Schedule instructions to minimize stalls when an execution unit is busy.
Avoid using serializing instructions.
Schedule instructions to avoid dispatch stalls due to renamed resource limitations.
— Only five instructions can be in execute-complete stage at any one time.
— Only five GPR destinations can be in execute-complete-deallocate stage at any
one time. Note that load with update address instructions use two destination
registers.
— Only four FPR destinations can be in execute-complete-deallocate stage at any
one time.
7.6.1
Branch, Dispatch, and Completion Unit Resource
Requirements
This section describes the specific resources required to avoid stalls during branch
resolution, instruction dispatching, and instruction completion.
7.6.1.1
Branch Resolution Resource Requirements
The following is a list of branch instructions and the resources required to avoid stalling the
fetch unit in the course of branch resolution:
The
bclr
instruction requires LR availability.
The
bcctr
instruction requires CTR availability.
Branch and link instructions require shadow LR availability.
The branch conditional on counter decrement and CR condition requires CTR
availability or the CR condition must be false, and the G2 core cannot be executing
instructions following an unresolved predicted branch when the branch is
encountered by the BPU.
The branch conditional on CR condition cannot be executed following an
unresolved predicted branch instruction.
F
Freescale Semiconductor, Inc.
n
.