
5-18
G2 PowerPC Core Reference Manual
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MOTOROLA
Exception Definitions
except an instruction at the point of completion, the time needed to drain the
completed store queue (see Section 7.1, “Terminology and Conventions,” for the
definition), and the time waiting for a correct empty state so that a valid MSR[IP]
may be saved. For lower-priority externally-generated interrupts, a delay may be
incurred waiting for another interrupt generated while reaching a recoverable state
to be serviced.
Further delays are possible for other types of exceptions depending on the number and type
of instructions that must be completed before those exceptions may be serviced. See
Section 5.1.2, “Summary of Front-End Exception Handling,” to determine possible
maximum latencies for different exceptions.
5.5
Exception Definitions
Table 5-9 shows all the types of exceptions that can occur with the G2 core and the MSR
bit settings when the processor transitions to supervisor mode. The state of these bits prior
to the exception is typically stored in SRR1 (or CSRR1 for critical interrupts on the G2_LE
core). Note that MSR[CE] is cleared for the following exceptions in system reset, machine
check, and critical interrupt.
Table 5-9. MSR Setting Due to Exception
Exception Type
MSR Bit
POW
TGPR
ILE
EE
PR
FP
ME
FE0
SE
BE
FE1 CE
1
IP
IR
DR
RI
LE
System reset
0
0
—
0
0
0
—
0
0
0
0
0
1
0
0
0
ILE
Machine check
0
0
—
0
0
0
0
0
0
0
0
0
—
0
0
0
ILE
DSI
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
ISI
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
External
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
Alignment
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
Program
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
Floating-point
unavailable
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
Decrementer
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
Critical Interrupt
0
0
—
0
0
0
—
0
0
0
0
0
—
0
0
0
ILE
System call
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
Trace exception
0
0
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
ITLB miss
0
1
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
DTLB miss on
load
0
1
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
DTLB miss on
store
0
1
—
0
0
0
—
0
0
0
0
—
—
0
0
0
ILE
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