
3-32
G2 PowerPC Core Reference Manual
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MOTOROLA
Instruction Set Summary
Note that any cache control instruction that generates an effective address that corresponds
to a direct-store segment (SR[T] = 1) is treated as a no-op.
Table 3-28 lists the cache instructions that are accessible to user-level programs.
Note that incoherency may occur if a write-through store is followed by a
dcbz
instruction
that is, in turn, followed by a snoop, all to the same cache block. This occurs when the
logical address for the
dcbz
and the write-through store are different, but aliased to the same
physical page.
To avoid potential adverse effects,
dcbz
should not address write-through memory that can
be accessed through multiple logical addresses. Explicit store instructions that write all
zeros should be used instead.
Note that broadcasting a sequence of
dcbz
instructions may cause snoop accesses to be
retried indefinitely, which may cause the snoop originator to time out or the snooped
transaction to not complete. This can be avoided by disabling the broadcasting of
dcbz
by
marking the memory space being addressed by the
dcbz
instruction as not global in the
BAT or PTE.
Note that incoherency may occur if the following sequence of accesses hits the same cache
block: a write-through, a
dcbz
instruction, a snoop. This occurs when the logical address
for the
dcbz
and the write-through store are different, but aliased to the same physical page.
3.2.5.4
External Control Instructions
The
eciwx
instruction provides an alternative way to map special devices. The MMU
translation of the EA is not used to select the special device, as it is used in loads and stores.
Rather, it is used as an address operand that is passed to the device over the address bus.
Four other signals (the burst and size signals on the 60x bus) are used to select the device;
these four signals output the 4-bit resource ID (RID) field in the EAR register. The
eciwx
instruction also loads a word from the data bus that is output by the special device.
Executing these instructions when MSR[DR] = 0 causes a programming error, and the
physical address on the bus is undefined. Executing these instructions to a direct-store
segment causes a DSI exception. The external control instructions are listed in Table 3-29.
3.2.6
PowerPC OEA Instructions
The OEA includes the structure of the memory management model, supervisor-level
registers, and exception model.
Table 3-29. External Control Instructions
Name
Mnemonic
Operand Syntax
External Control In Word Indexed
eciwx
rD,rA,rB
External Control Out Word Indexed
ecowx
r
S
,r
A
,r
B
F
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n
.