
MOTOROLA
Chapter 5. Exceptions
5-15
Exception Processing
Asynchronous, maskable exceptions (that is, the external, system management, and
decrementer interrupts) are enabled by setting the MSR[EE] bit. When
MSR[EE] = 0, recognition of these exception conditions is delayed. MSR[EE] is
cleared automatically when an exception is taken, to delay recognition of conditions
causing those exceptions.
A machine check exception can occur only if the machine check enable bit,
MSR[ME], is set. If MSR[ME] is cleared, the processor goes directly into checkstop
state when a machine check exception condition occurs. Individual machine check
exceptions can be enabled and disabled through bits in the HID0 register, as
described in Table 2-5.
The G2_LE core enables the critical interrupt with the MSR[CE] bit.
System reset exceptions cannot be masked.
5.2.3
Steps for Exception Processing
After it is determined that the exception can be taken (by confirming that any
instruction-caused exceptions occurring earlier in the instruction stream have been handled,
and by confirming that the exception is enabled for the exception condition), the processor
does the following:
1. The machine status save/restore register 0 (SRR0) is loaded with an instruction
address that depends on the type of exception. See the individual exception
description for details about how this register is used for specific exceptions.
2. SRR1[1–4, 10–15] are loaded with information specific to the exception type.
3. SRR1[5–9, 16–31] are loaded with a copy of the corresponding bits of the MSR.
4. The MSR is set as described in Table 5-7. The new values take effect beginning
with the fetching of the first instruction of the exception-handler routine located at
the exception vector address.
Note that MSR[IR] and MSR[DR] are cleared for all exception types; therefore,
address translation is disabled for both instruction fetches and data accesses
beginning with the first instruction of the exception-handler routine.
5. Instruction fetch and execution resumes, using the new MSR value, at a location
specific to the exception type. The location is determined by adding the exception's
vector (see Table 5-2) to the base address determined by MSR[IP]. If IP is cleared,
exceptions are vectored to the physical address 0x000
n_nnnn
. If IP is set,
exceptions are vectored to the physical address 0xFFF
n_nnnn
. For a machine check
exception that occurs when MSR[ME] = 0 (machine check exceptions are
disabled), the processor enters the checkstop state (the machine stops executing
instructions). See Section 5.5.2, “Machine Check Exception (0x00200).”
Note that the same steps occur when a critical interrupt occurs (and is enabled) for the
G2_LE core, except that CSRR0 is set instead of SRR0 and CSRR1 is set instead of SRR1.
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