
MOTOROLA
Chapter 4. Instruction and Data Cache Operation
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4-17
Cache Coherency—MEI Protocol
Figure 4-4. MEI Cache Coherency Protocol—State Diagram (WIM = 001)
Section 4.11, “MEI State Transactions,” provides a detailed list of MEI transitions for
various operations and WIM bit settings.
4.7.3
MEI Hardware Considerations
While the G2 core provides the hardware required to monitor bus traffic for coherency, the
G2 core data cache tags are single ported, and a simultaneous load or store and snoop access
represent a resource conflict. In general, the snoop access has highest priority and is given
first access to the tags. The load or store access will then occur on the clock following the
snoop. The snoop is not given priority into the tags when the snoop coincides with a tag
write (for example, validation after a cache block load). In these situations, the snoop is
retried and must re-arbitrate before the lookup is possible.
Occasionally, cache snoops cannot be serviced and must be retried. These retries occur if
the cache is busy with a burst read or write when the snoop operation takes place.
Note that it is possible for a snoop to hit a modified cache block that is already in the process
of being written to the copy-back buffer for replacement purposes. If this happens, the G2
RH
WH
Bus Transactions
RH
SH
SH/CIR
WM
SH/CRW
RM
SH/CRW
SH = Snoop Hit
RH = Read Hit
RM = Read Miss
WH = Write Hit
WM = Write Miss
SH/CRW = Snoop Hit, Cacheable Read/Write
SH/CIR = Snoop Hit, Cache Inhibited Read
= Cache Line Fill
= Snoop Push
WH
Exclusive
Modified
Invalid
F
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