
4-36
G2 PowerPC Core Reference Manual
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MOTOROLA
Cache Locking
mfmsr
lis
ori
and
mtmsr
sync
r1
r2, 0xFFFF
r2, r2, 0x667F
r1, r1, r2
r1
4.12.3.1.4 Invalidating the Data Cache
If a non-empty data cache has modified data, and the data cannot be discarded, the data
cache must be flushed before it can be invalidated. Data cache flushing is accomplished by
filling the data cache with known data and performing a flash invalidate or a series of
dcbf
instructions that force a flush and invalidation of the data cache block.
The following code sequence shows how to flush the data cache:
# r6 contains a block-aligned address in memory with which to fill
# the data cache. For this example, address 0x0 is used
li r6, 0x0
# CTR = number of data blocks to load
# Number of blocks = (16K) / (32 Bytes/block)
#
li r1, 0x200
mtctr r1
= 2^14 / 2^5 = 2^9 = 0x200
# Save the total number of blocks in cache to r8
mr r8, r1
# Load the entire cache with known data
loop:
lwz r2, 0(r6)
addi r6, r6, 32 # Find the next block
bdnz loop # Decrement the counter, and
# branch if CTR != 0
# Now, flush the cache with dcbf instructions
li r6, 0x0 # Address of first block
mtctr r8 # Number of blocks
loop2:
dcbf r0, r6
addi r6, r6, 32 # Find the next block
bdnz loop2 # Decrement the counter, and
# branch if CTR != 0
If the content of the data cache does not need to be flushed to memory, the cache can be
directly invalidated. The entire data cache is invalidated through the data cache flash
invalidate bit HID0[DCFI], bit 21. Setting HID0[DCFI] and then immediately clearing it
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n
.