
Contents
Paragraph
Number
Title
Page
Number
MOTOROLA
Contents
xix
9.9
9.9.1
9.10
IEEE 1149.1-Compliant Interface......................................................................9-42
IEEE 1149.1 Interface Description................................................................9-42
Using core_dbwo (Data Bus Write Only)..........................................................9-43
Chapter 10
Power Management
10.1
10.2
10.3
10.3.1
10.3.1.1
10.3.1.2
10.3.1.3
10.3.1.4
10.3.1.5
10.3.2
10.4
Overview............................................................................................................10-1
Dynamic Power Management............................................................................10-1
Programmable Power Modes.............................................................................10-2
Power Management Modes ...........................................................................10-3
Full-Power Mode with DPM Disabled......................................................10-3
Full-Power Mode with DPM Enabled.......................................................10-3
Doze Mode.................................................................................................10-3
Nap Mode ..................................................................................................10-4
Sleep Mode................................................................................................10-5
Power Management Software Considerations...............................................10-6
Example Code Sequence for Entering Processor Sleep Mode..........................10-6
Chapter 11
Debug Features
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.3
11.4
11.5
11.6
Breakpoint Facilities.......................................................................................... 11-1
Instruction Address Breakpoint Registers (IABR, IABR2)........................... 11-1
Instructional Address Control Register (IBCR)............................................. 11-2
Data Address Breakpoint Registers (DABR, DABR2)................................. 11-2
Data Address Control Register (DBCR)........................................................ 11-3
Other Debug Resources................................................................................. 11-3
Software Debug Features............................................................................... 11-3
Expanded Debugging Facilities in Breakpoint Registers.................................. 11-4
Breakpoint Enabled........................................................................................ 11-4
Single-Step Enabled....................................................................................... 11-4
Branch Trace Enabled.................................................................................... 11-5
Address Matching.......................................................................................... 11-5
Combinational Matching ............................................................................... 11-5
Watchpoint Signaling......................................................................................... 11-5
Exception Vectors and Priority.......................................................................... 11-6
Instruction Address Breakpoint Examples ........................................................ 11-6
Synchronization Requirements.......................................................................... 11-8
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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