
MOTOROLA
Chapter 2. Register Model
2-19
Register Set
Figure 2-10. Lower BAT Register
The BAT registers contain the effective-to-physical address mappings for blocks of
memory. This mapping includes the effective address bits that are compared with the
effective address of the access, the memory/cache access mode bits (WIMG), and the
protection bits for the block. The size of the block and the starting address of the block are
defined by the physical block number (BRPN) and block size mask (BL) fields.
The sixteen new BAT registers are enabled by HID2[HBE]. However, regardless of the
setting of this bit, the BAT registers are accessible by the
mfspr
and
mtspr
instructions and
are only accessible to supervisor-level programs. See Section 2.1.2.3, “Hardware
Implementation Register 2 (HID2),” for more information on the HBE bit.
2.1.2.9
Critical Interrupt Save/Restore Register 0 (CSRR0)—G2_LE
Only
CSRR0 is used to save machine status on critical interrupt exceptions and restore machine
status when an
rfci
instruction is executed. The format of CSRR0 is shown in Figure 2-11.
Figure 2-11. Critical Interrupt Save/Restore Register 0 (CSRR0)
For information on how specific exceptions affect CSRR0, refer to the descriptions of
individual exceptions in Chapter 5, “Exceptions.”
2.1.2.10 Critical Interrupt Save/Restore Register 1 (CSRR1)—G2_LE
Only
CSRR1 is used to save machine status on exceptions and to restore machine status when an
rfci
instruction is executed. Figure 2-12 shows the CSRR1 format.
Figure 2-12. Critical Interrupt Save/Restore Register 1 (CSRR1)
For information on how specific exceptions affect CSRR1, refer to the individual
exceptions in Chapter 5, “Exceptions.”
0
*W and G bits are not defined for IBAT registers. Attempting to write to these bits causes boundedly-undefined results.
14 15
24 25
28 29 30
31
BRPN
0 0000 0000 0
WIMG*
0
PP
Reserved
CSRR0
0
29 30 31
00
Reserved
0
CSRR1
0
31
F
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.