
MOTOROLA
Chapter 6. Memory Management
6-9
MMU Features
Figure 6-4. Address Translation Types
Block address translation occurs in parallel with page address translation and is similar to
page address translation; however, fewer higher-order effective address bits are translated
into physical address bits (more lower-order address bits (at least 17) are untranslated to
form the offset into a block). Also, instead of segment descriptors and a TLB, block address
translations use the on-chip BAT registers as a BAT array. If an effective address matches
the corresponding field of a BAT register, the information in the BAT register is used to
generate the physical address; in this case, the results of the page translation (occurring in
parallel) are ignored (even if the segment corresponds to the direct-store interface space).
Real addressing mode translation occurs when address translation is disabled; in this case,
the physical address generated is identical to the effective address. Instruction and data
address translation is enabled with the MSR[IR] and MSR[DR] bits, respectively. Thus,
when the processor generates an access, and the corresponding address translation enable
(T = 1)
(T = 0)
0
31
Effective Address
0
51
Virtual Address
Segment Descriptor
Located
Match with BAT
Registers
0
31
Physical Address
0
31
Physical Address
0
31
Physical Address
Look Up in
Page Table
Address Translation Disabled
(MSR[IR] = 0 or MSR[DR] = 0)
Page Address
Translation
Direct-Store Interface
Translation
Real Addressing Mode
Effective Address = Physical Address
(see Section 6.2, “Real Addressing
Mode”)
Block Address Translation
(see Section 6.3, “Block
Address Translation”)
DSI/ISI Exception
F
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