
3-34
G2 PowerPC Core Reference Manual
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MOTOROLA
Instruction Set Summary
For
mtspr
and
mfspr
instructions, the SPR number coded in assembly language does not
appear directly as a 10-bit binary number in the instruction. The number coded is split into
two 5-bit halves that are reversed in the instruction encoding, with the high-order 5 bits
appearing in bits 16–20 of the instruction encoding and the low-order 5 bits in bits 11–15.
If the SPR field contains any value other than one of the values shown in Table 3-33, either
the program exception handler is invoked or the results are boundedly undefined.
Table 3-32. Move To/From Special-Purpose Register Instructions
Name
Mnemonic
Operand Syntax
Move from Special-Purpose Register
mfspr
r
D
,
SPR
Move to Special-Purpose Register
mtspr
SPR
,r
S
Table 3-33. Implementation-Specific SPR Encodings (mfspr)
SPR
1
Register Name
Access
Decimal
spr[5–9]
spr[0–4]
58
00001
11010
CSRR0
2
Supervisor
59
00001
11011
CSRR1
2
Supervisor
276
01000
10100
SPRG4
2
Supervisor
277
01000
10101
SPRG5
2
Supervisor
278
01000
10110
SPRG6
2
Supervisor
279
01000
10111
SPRG7
2
Supervisor
286
01000
11110
SVR
2
Supervisor
309
01001
10101
IBCR
2
Supervisor
310
01001
10110
DBCR
2
Supervisor
311
01001
10111
MBAR
2
Supervisor
317
01001
11101
DABR2
2
Supervisor
560
10001
10000
IBAT4U
2
Supervisor
561
10001
10001
IBAT4L
2
Supervisor
562
10001
10010
IBAT5U
2
Supervisor
563
10001
10011
IBAT5L
2
Supervisor
564
10001
10100
IBAT6U
2
Supervisor
565
10001
10101
IBAT6L
2
Supervisor
566
10001
10110
IBAT7U
2
Supervisor
567
10001
10111
IBAT7L
2
Supervisor
568
10001
11000
DBAT4U
2
Supervisor
569
10001
11001
DBAT4L
2
Supervisor
570
10001
11010
DBAT5U
2
Supervisor
571
10001
11011
DBAT5L
2
Supervisor
F
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