
5-20
G2 PowerPC Core Reference Manual
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MOTOROLA
Exception Definitions
A hard reset has the highest priority of any exception, and is always nonrecoverable.
Table 5-11 shows the state of the machine just before it fetches the first instruction of the
system reset handler after a hard reset.
The core_hreset signal can be asserted for the following reasons:
System power-on reset
System reset from a panel switch
For information on the core_hreset signal, see Section 8.3.10.1, “Hard Reset
(core_hreset)—Input.”
The following is also true after a hard reset operation:
External checkstops are enabled
Table 5-10. Hard Reset MSR Value and Exception Vector
core_msrip
MSR[0–31]
Fetch Instructions from Handler
at System Reset Vector
asserted
0x0000_0040 (MSR[IP] = 1)
0xFFF0_0100
negated
0x0000_0000 (MSR[IP] = 0)
0x0000_0100
Table 5-11. Settings Caused by Hard Reset
Register
Setting
Register
Setting
GPRs
Unknown
PVR
See Table 2-3
FPRs
Unknown
HID0
0000_0000
FPSCR
00000000
HID1
0000_0000
CR
All 0s
HID2
0000_0000 or 0800_0000
SRs
Unknown
DMISS and IMISS
All 0s
MSR
0000_0040 or 0000_0000 or
0001_0041 or 0001_0001
DCMP and ICMP
All 0s
XER
0000_0000
RPA
All 0s
TBU
0000_0000
IABR
All 0s
TBL
0000_0000
DSISR
0000_0000
LR
0000_0000
DAR
0000_0000
CTR
0000_0000
DEC
FFFF_FFFF
SDR1
0000_0000
HASH1
0000_0000
SRR0 (and CSRR0)
0000_0000
HASH2
0000_0000
SRR1 (and CSRR1)
0000_0000
TLBs
Unknown
SPRGs
0000_0000
Cache
All cache blocks invalidated
Tag directory
All 0s. (However, LRU bits are
initialized so each side of the
cache has a unique LRU value.)
BATs
Unknown
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