
MOTOROLA
Chapter 6. Memory Management
6-19
Real Addressing Mode
Note that the G2 core contains other features that do not specifically control the MMU, but
are implemented to increase performance and flexibility. These are:
Complete set of shadow segment registers for the instruction MMU. These registers
are invisible to the programming model, as described in Section 6.4.3, “TLB
Description.”
Temporary GPR0–GPR3. These registers are available as
r0
–
r3
when MSR[TGPR]
is set. The core automatically sets MSR[TGPR] whenever one of the three TLB miss
exceptions occurs, allowing these exception handlers to have four registers that are
used as scratchpad space, without having to save or restore this part of the machine
state that existed when the exception occurred. Note that MSR[TGPR] is restored to
the value in SRR1 when the
rfi
instruction is executed. Refer to Section 6.5.2,
“Implementation-Specific Table Search Operation,” for code examples that take
advantage of these registers.
In addition, the G2 core also automatically saves the values of CR[CR0] of the executing
context to SRR1[0–3] whenever one of the three TLB miss exceptions occurs. Thus, the
exception handler can set CR[CR0] bits and branch accordingly in the exception handler
routine, without having to save the existing CR[CR0] bits. However, the exception handler
must restore these bits to CR[CR0] before executing the
rfi
instruction. There are also four
other bits saved in SRR1 whenever a TLB miss exception occurs that give information
about whether the access was an instruction or data access; and if it was a data access,
whether it was for a load or a store instruction. Also, these bits give some information
related to the protection attributes for the access, and which set in the TLB will be replaced
when the next TLB entry is loaded. Refer to Section 6.5.2.1, “Resources for Table Search
Operations,” for more information on these bits and their use.
6.2
Real Addressing Mode
If address translation is disabled (MSR[IR] = 0 or MSR[DR] = 0) for a particular access,
the effective address is treated as the physical address and is passed directly to the memory
Instruction and data PTE
compare registers
(ICMP and DCMP)
The ICMP and DCMP registers contain the word to be compared with the first word of
a PTE in the table search software routine to determine if a PTE contains the address
translation for the instruction or data access. The contents of ICMP and DCMP are
automatically derived by the core when a TLB miss exception occurs.
These registers are implementation-specific.
Required physical address
register (RPA)
The system software loads a TLB entry by loading the second word of the matching
PTE entry into the RPA register and then executing the
tlbli
or
tlbld
instruction (for
loading the ITLB or DTLB, respectively).
This register is implementation-specific.
Table 6-6. MMU Registers (continued)
Register
Description
F
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n
.