
8-10
G2 PowerPC Core Reference Manual
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MOTOROLA
Signal Descriptions
8.3
Signal Descriptions
This section describes individual G2 core signals, grouped according to Figure 8-1. Note
that the following sections are intended to provide a quick summary of signal functions.
Chapter 9, “Core Interface Operation,” describes many of these signals in greater detail,
both with respect to how individual signals function and how groups of signals interact.
Figure 8-3 shows the G2 core signals groups in greater detail. However, it does not show
both the input and output versions of the signals, their directions (input/output), and the
associated input/output enable signals.
Figure 8-3. Detailed Signal Groups
core_tck
core_tdi
core_smi
core_mcp
core_dp[0:7]
core_dpe
core_a[0:31]
core_ap[0:3]
core_cse[0:1]
core_aack
core_artry
G2 Core
+1.5 V
core_abb
core_bg
core_br
core_ci
core_wt
core_clk
core_pll_cfg[0:4]
core_ckstp
core_d
core_dabr
1
/dabr 2
1
core_dbb
core_dbg
core_dbwo
core_dbdis
core_disable
core_tap_en
core_tlmsel
core_dl,core_dh
core_drtry
core_tea
core_tle
1
core_outputs
core_gbl
core_hreset
core_sreset
core_32bitmode
core_iabr/iabr2
1
core_l1/l2_tstclk
core_lssd_mode
core_tc[0:1]
core_msrip
core_drtrymode
core_redpinmode
core_rsrv
core_tben
core_tlbisync
core_svr
1
core_sysclk
core_ta
core_tbst
core_tdo
core_tms
core_trst
core_tsiz[0:2]
core_qack
core_qreq
core_ape
core_tt
core_ts
Address Arbitration
Address Start
Address Bus
Transfer Attribute
Address Termination
Clocks
Data Arbitration
Data Transfer
Data Termination
Processor Status
JTAG/COP Interface
1
G2_LE specific signal.
Test Interface
Debug Control
core_int
core_cint
1
Interrupt,
Checkstop
Reset/Reset Config.
F
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