
MOTOROLA
Chapter 2. Register Model
2-15
Register Set
implementation-specific special purpose register (SPR) which is accessed as SPR1011
(decimal). The HID2 bits are shown in Table 2-8.
Figure 2-4. Hardware Implementation-Dependent Register 2 (HID2)
Table 2-8 describes the HID2 fields.
Table 2-8. HID2 Bit Descriptions
Bits
Name
Description
0–3
—
Reserved
4
LET
True little-endian. This bit enables true little-endian mode operation for instruction and data
accesses. This bit is set to reflect the state of the core_tle signal at the negation of
core_hreset. This bit is used in conjunction with MSR[LE] to determine the endian mode of
operation as described in Table 1-1.
0 Modified (PowerPC) little-endian mode
1 True little-endian mode
Changing the value of this bit during normal operation is discouraged
5–12
—
Reserved
13
HBE
High BAT enable. Regardless of the setting of HID2[HBE], these BATs are accessible by
mfspr
and
mtspr
.
0 IBAT[4–7] and DBAT[4–7] are disabled
1 IBAT[4–7] and DBAT[4–7] are enabled
14
—
Reserved
15
—
Reserved
16–18
IWLCK[0–2]
Instruction cache way-lock. Useful for locking blocks of instructions into the instruction cache
for time-critical applications that require deterministic behavior. See Chapter 4, “Instruction
and Data Cache Operation.”
000 = no ways locked
001 = way 0 locked
010 = way 0 through way 1 locked
011 = way 0 through way 2 locked
100 = way 0 through way 3 locked
101 = way 0 through way 4 locked
110 = way 0 through way 5 locked
111 = Reserved
19–23
—
Reserved
31
27
26
24
23
19
18
14
13
12
4
0
IWLCK[0–2]
0
0
0
0
0
0
0
0
0
0
HBE
DWLCK[0–2]
0
0
0
0
0
0
0
0
3
5
0
0
LET
15
0
0
0
16
Reserved
0
0
F
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.