
6-24
G2 PowerPC Core Reference Manual
For More Information On This Product,
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MOTOROLA
Memory Segment Model
instruction, and by the cache management instructions that are treated as a load with respect
to address translation. Similarly, store operations include those operations generated by
store instructions, by the
ecowx
instruction, and by the cache management instructions that
are treated as a store with respect to address translation. In the columns for the G2 core, the
combination of the core itself and the software used to search the page tables (described in
Section 6.5.2, “Implementation-Specific Table Search Operation”) is assumed.
For more information, see “Page History Recording” in Chapter 7, “Memory
Management,” of the
Programming Environments Manual
.
6.4.2
Page Memory Protection
The G2 core implements page memory protection as it is defined in Chapter 7, “Memory
Management,” in the
Programming Environments Manual
.
Table 6-8. Model for Guaranteed R and C Bit Settings
Priority
Scenario
R Bit Set
C Bit Set
OEA
G2 Core
OEA
G2 Core
1
No-execute protection violation
No
No
No
No
2
Page protection violation
Maybe
Yes
No
No
3
Out-of-order instruction fetch or load operation
Maybe
No
No
No
4
Out-of-order store operation for instructions that will
cause no other kind of precise exception (in the
absence of system-caused, imprecise, or floating-point
assist exceptions
Maybe
1
1
If C is set, R is guaranteed to also be set.
2
This includes the case when the instruction was fetched out-of-order and R was not set (does not apply for the G2
core).
3
The
dcbi
instruction should never be used on the G2 core.
No
No
No
5
All other out-of-order store operations
Maybe
1
No
Maybe
1
No
6
Zero-length load (
lswx
)
Maybe
Yes
No
No
7
Zero-length store (
stswx
)
Maybe
1
Yes
Maybe
1
Yes
8
Store conditional (
stwcx.
) that does not store
Maybe
1
Yes
Maybe
1
Yes
9
In-order instruction fetch
Yes
2
Yes
No
No
10
Load instruction or
eciwx
Yes
Yes
No
No
11
Store instruction,
ecowx
or
dcbz
instruction
Yes
Yes
Yes
Yes
12
dcbt
,
dcbtst
,
dcbst
, or
dcbf
instruction
Maybe
Yes
No
No
13
icbi
instruction
Maybe
1
No
No
1
No
14
dcbi
3
instruction
Maybe
1
Yes
Maybe
1
Yes
F
Freescale Semiconductor, Inc.
n
.