
MOTOROLA
Chapter 7. Instruction Timing
7-7
Instruction Timing Overview
In dispatch entry (IQ0/IQ1)—Instructions can be dispatched from IQ0 and
IQ1. Because dispatch is instantaneous, it is perhaps more useful to describe
it as an event that marks the point in time between the last cycle in the fetch
stage and the first cycle in the execute stage.
Execute—The operations specified by an instruction are being performed by
the appropriate execution unit. The black stripe is a reminder that the
instruction occupies an entry in the CQ, described in Figure 7-3.
Complete—The instruction is in the CQ. In the final stage, the results of the
executed instruction are written back and the instruction is retired. The CQ
has five entries, CQ0–CQ4.
In retirement entry—Completed instructions can be retired from CQ0 and
CQ1. Like dispatch, retirement is an event that in this case occurs at the end
of the final cycle of the complete stage.
Figure 7-3 shows the stages of G2 core execution units.
Figure 7-3. G2 Core Processor Pipeline Stages
Fetch
In Dispatch
Entry
Execute
1
Complete/Retire
Fetch
In Dispatch
Entry
Complete/Retire
EA
Fetch
Complete/Retire
IU/SRU Instructions
LSU Instructions
FPU Instructions
Normalize
Multiply
Add
Round/
Execute
Execute
Calculation Cache
Align
BPU Instructions
Fetch
Fetch
Predict
Complete/Retire
2
In Dispatch
Entry
In Completion
Queue
2
1
Several integer instructions, such as multiply and divide instructions, require
multiple cycles in the execute stage.
2
Only those branch instructions that update the LR or CTR take an entry in the
completion queue.
In Dispatch
Entry
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