
MOTOROLA
Appendix B. Revision History
B-1
Appendix B
Revision History
This appendix provides a list of the major differences between the
G2 PowerPC Core
Reference Manual
, Revision 0 and the
G2 PowerPC Core Reference Manual
, Revision 1.
B.1
Revision Changes From Revision 0 to Revision 1
Major changes to the
G2 PowerPC Core Reference Manual
from Revision 0 to Revision 1
are as follows:
Section, Page
Book
Changes
Added trademark information for PowerPC.
Added tab pages, Glossary, Appendix B, and Index.
Under the heading ‘Organization,’ in the first bullet, replace the
statement in parenthesis in the second sentence with the following:
(including instruction and data cache way-locking for the G2 core)
Cache way-locking is a feature of both the G2 core and the G2_LE.
Remove ‘G2_LE-Only’ from the heading and replace the paragraph
with the following:
The G2 core implements instruction and data cache way-locking,
which guarantees that certain memory accesses will hit in the cache.
This provides deterministic access times for those accesses. See
Chapter 4, “Instruction and Data Cache Operation,” for more
information.
In Table 1-6, “Differences Between G2 and G2_LE Cores,” replace
the rows on cache locking with the following:
xxv
1.3.3.3, 1-26
1.4, 1-40
Supports instruction cache
way-locking in addition to
entire instruction cache
locking
HID2 register controls instruction cache way-locking. The
instruction cache way-locking is useful for locking blocks of
instructions into the instruction cache for time-critical
applications that require deterministic behavior.
Supports data cache
way-locking in addition to
entire data cache locking
HID2 register controls data cache way-locking. It is useful
for locking blocks of data into the data cache for
time-critical applications where deterministic behavior is
required.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.