
5-4
G2 PowerPC Core Reference Manual
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MOTOROLA
Exception Classes
Table 5-2. Exceptions and Conditions
Exception Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
—
System reset
00100
A system reset is caused by the assertion of either core_sreset or core_hreset.
Machine check
00200
A machine check is caused by the assertion of the core_tea signal during a data
bus transaction, assertion of core_mcp, or an address or data parity error.
DSI
00300
The cause of a DSI exception can be determined by the bit settings in the DSISR,
listed as follows:
1 Set if the translation of an attempted access is not found in the primary hash
table entry group (HTEG), or in the rehashed secondary HTEG, or in the range
of a DBAT register; otherwise cleared.
4
Set if a memory access is not permitted by the page or DBAT protection
mechanism; otherwise cleared.
5
Set by an
eciwx
or
ecowx
instruction if the access is to an address that is
marked as write-through, or execution of a load/store instruction that
accesses a direct-store segment.
6
Set for a store operation and cleared for a load operation
9
G2_LE core only. Set a data address breakpoint exception occurs when the
data [0–28] in the DABR or DABR2 matches the next data access (load or
store instruction) to complete in the completion unit. The different breakpoints
are enabled as follows:
Write breakpoints enabled when DABR[30] is set
Read breakpoints enabled when DABR[31] is set
11 Set if
eciwx
or
ecowx
is used and EAR[E] is cleared
ISI
00400
An ISI exception is caused when an instruction fetch cannot be performed for any
of the following reasons:
The effective (logical) address cannot be translated. That is, there is a page
fault for this portion of the translation, so an ISI exception must be taken to load
the PTE (and possibly the page) into memory.
The fetch access is to a direct-store segment (indicated by SRR1[3] set)
The fetch access violates memory protection (indicated by SRR1[4] set). If the
key bits (Ks and Kp) in the segment register and the PP bits in the PTE are set
to prohibit read access, instructions cannot be fetched from this location.
External interrupt
00500
An external interrupt is caused when MSR[EE] = 1 and the core_int signal is
asserted.
Alignment
00600
An alignment exception is caused when the core cannot perform a memory
access for any of the reasons described below:
The operand of a floating-point load or store instruction is not word-aligned.
The operand of
lmw
,
stmw
,
lwarx
, and
stwcx.
instructions are not aligned.
The execution of a floating-point load or store instruction to a direct-store
segment.
The operand of a load, store, load multiple, store multiple, load string, or store
string instruction crosses a segment boundary into a direct-store segment, or
crosses a protection boundary.
Execution of a misaligned
eciwx
or
ecowx
instruction.
The instruction is
lmw
,
stmw
,
lswi
,
lswx
,
stswi
,
stswx
,
and the G2 core is in
little-endian mode. This applies to both modified little-endian and true
little-endian mode for G2_LE core.
The operand of
dcbz
is in memory that is write-through-required or
caching-inhibited.
F
Freescale Semiconductor, Inc.
n
.