
4-10
G2 PowerPC Core Reference Manual
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MOTOROLA
Memory Management/Cache Access Mode Bits—W, I, M, and G
Figure 4-3. Double-Word Address Ordering—Critical-Double-Word-First
4.5.3
Access to Direct-Store Segments
The G2 core does not provide support for access to direct-store segments. Operations
attempting to access a direct-store segment will invoke a DSI exception. See Section 5.5.3,
“DSI Exception (0x00300).”
4.6
Memory Management/Cache Access Mode
Bits—W, I, M, and G
Some memory characteristics can be set on either a block or page basis by using the WIMG
bits in the BAT registers or page table entry (PTE), respectively. The WIMG attributes
control the following functionality:
Write-through (W bit)
Caching-inhibited (I bit)
Memory coherency (M bit)
Guarded memory (G bit)
These bits allow both uniprocessor and multiprocessor system designs to exploit numerous
system-level performance optimizations.
Careless specification and use of these bits may create situations where coherency
paradoxes are observed by the processor. In particular, this can happen when the state of
these bits is changed without appropriate precautions being taken (for example, when
G2 Core Cache Address
Bits 27:28
0 0
Beat
Beat
A
B
C
D
0 1
1 0
1 1
A
B
C
D
0
1
2
3
If the address requested is in double-word A, the address placed on the bus is that of double-word A, and
the four data beats are ordered in the following manner:
If the address requested is in double-word C, the address placed on the bus will be that of double-word C,
and the four data beats are ordered in the following manner:
C
D
A
B
0
1
2
3
F
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