
MOTOROLA
Chapter 3. Instruction Set Model
3-35
Instruction Set Summary
Implementation Note
—The core ignores the extended opcode differences between
mftb
and
mfspr
by ignoring TB[25] and treating both instructions identically.
3.2.6.3
Memory Control Instructions—OEA
This section describes memory control instructions, which include the following types:
Cache management instructions
Segment register manipulation instructions
Translation lookaside buffer management instructions
572
10001
11100
DBAT6U
2
Supervisor
573
10001
11101
DBAT6L
Supervisor
574
10001
11110
DBAT7U
2
Supervisor
575
10001
11111
DBAT7L
2
Supervisor
976
11110
10000
DMISS
Supervisor
977
11110
10001
DCMP
Supervisor
978
11110
10010
HASH1
Supervisor
979
11110
10011
HASH2
Supervisor
980
11110
10100
IMISS
Supervisor
981
11110
10101
ICMP
Supervisor
982
11110
10110
RPA
Supervisor
1008
11111
10000
HID0
Supervisor
1009
11111
10001
HID1
Supervisor
1010
11111
10010
IABR
Supervisor
1011
11111
10011
HID2
Supervisor
1013
11111
10101
DABR
2
Supervisor
1018
11111
11010
IABR2
2
Supervisor
1
Note that the order of the two 5-bit halves of the SPR number is reversed
compared with actual instruction coding.
For
mtspr
and
mfspr
instructions, the SPR number coded in assembly
language does not appear directly as a 10-bit binary number in the instruction.
The number coded is split into two 5-bit halves that are reversed in the
instruction, with the high-order 5 bits appearing in bits 16–20 of the instruction
and the low-order 5 bits in bits 11–15.
2
These registers are implementation-specific for G2_LE core only.
Table 3-33. Implementation-Specific SPR Encodings (mfspr) (continued)
SPR
1
Register Name
Access
Decimal
spr[5–9]
spr[0–4]
F
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n
.