
MOTOROLA
Chapter 3. Instruction Set Model
3-1
Chapter 3
Instruction Set Model
This chapter describes the operand conventions as they are represented in two levels of the
PowerPC architecture. It also provides detailed descriptions of conventions used for storing
values in registers and memory, accessing the core registers, and the representation of data
in these registers.
Operand conventions
G2 core instruction set
3.1
Operand Conventions
This section describes the integer and floating-point operand conventions. It also describes
the big- and little-endian byte ordering for the G2 and G2_LE cores.
3.1.1
Data Organization in Memory and Memory Operands
Bytes in memory are numbered consecutively starting with 0. Each number is the address
of the corresponding byte.
Memory operands may be bytes, half words, words, or double words, or, for the load/store
multiple and move assist instructions, a sequence of bytes or words. The address of a
memory operand is the address of its first byte (that is, of its lowest-numbered byte).
Operand length is implicit for each instruction.
3.1.2
Endian Modes and Byte Ordering
The PowerPC architecture supports both big- and little-endian byte ordering. The default
byte and bit ordering is big-endian. See Section 3.1.2, “Byte Ordering,” in the
Programming Environments Manual
, for more information about big- and little-endian
byte ordering.
True little-endian mode is supported in the G2_LE core to minimize the impact on software
porting from true little-endian systems. The true little-endian mode applies for all
instruction fetches and data load and store operations to and from memory. The G2_LE
powers up in one of two endian modes, big-endian mode or true little-endian mode, selected
by the core_tle signal at the negation of core_hreset. The endian mode should be set at the
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