
MOTOROLA
Chapter 7. Instruction Timing
7-25
Instruction Scheduling Guidelines
7.6.1.2
Dispatch Unit Resource Requirements
The following is a list of resources required to avoid stalls in the dispatch unit. Note that
the two dispatch buffers, IQ0 and IQ1, are at the bottom of the instruction queue:
Requirements for dispatching from IQ0 are as follows:
— Needed execution unit available
— Needed GPR rename registers available
— Needed FPR rename registers available
— Completion queue is not full
— Instruction is dispatch serialized and completion buffer is empty
— A dispatch serialized instruction is not currently being executed
Requirements for dispatching from IQ1 are as follows:
— Instruction in IQ0 must dispatch
— Instruction dispatched by IQ0 is not dispatch serialized
— Needed execution unit is available (after dispatch from IQ0)
— Needed GPR rename registers are available (after dispatch from IQ0)
— Needed FPR rename register is available (after dispatch from IQ0)
— Completion queue is not full (after dispatch from IQ0)
— Instruction dispatched from IQ1 is not dispatch serialized
7.6.1.3
Completion Unit Resource Requirements
The following is a list of resources required to avoid stalls in the completion unit; note that
the two completion buffers are described as CQ0 and CQ1, where CQ0 is the entry at the
end of the completion queue:
Requirements for completing an instruction from CQ0 are as follows:
— Instruction in CQ0 must be finished
— Instruction in CQ0 must not follow an unresolved predicted branch
— Instruction in CQ0 must not cause an exception
Requirements for completing an instruction from CQ1 are as follows:
— Instruction in CQ0 must complete in same cycle
— Instruction in CQ1 must be finished
— Instruction in CQ1 must not follow an unresolved predicted branch
— Instruction in CQ1 must not cause an exception
— Instruction in CQ1 must be an integer or load instruction
— Number of CR updates from both CQ0 and CQ1 must not exceed one
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