
2-22
G2 PowerPC Core Reference Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Register Set
Figure 2-15. Instruction Address Breakpoint Control Register (IBCR)
Table 2-14 describes the IBCR fields.
2.1.2.15 Data Address Breakpoint Register (DABR and
DABR2)—G2_LE Only
The optional data address breakpoint facility on the G2_LE core is controlled by optional
SPRs, DABR and DABR2. The data address breakpoint facility provides a means to detect
data accesses to a designated double-word address. The breakpoint address is compared to
the effective address of all data accesses; it does not apply to instruction fetches.
DABR and DABR2, the two data address breakpoint registers shown in Figure 2-16, can
both cause the data address breakpoint exception.
Figure 2-16. Data Address Breakpoint Registers (DABR and DABR2)
Table 2-14. Instruction Address Breakpoint Control Registers (IBCR)
Bits
Name
Description
0–7
—
Reserved
8–9
CMP
IABR breakpoint compare type
00 Match if instruction’s EA equals IABR[CEA]
01 Reserved
10 Match if instruction’s EA is less than IABR[CEA]
11 Match if instruction’s EA is greater than or equal to IABR[CEA]
10–11
CMP2
IABR2 breakpoint compare type
00 Match if instruction’s EA equals IABR2[CEA]
01 Reserved
10 Match if instruction’s EA less than IABR2[CEA]
11 Match if instruction’s EA greater than or equal to IABR2[CEA]
12
—
Reserved
13
—
Reserved
14
SIG_TYPE
Combinational signal type
0 Instruction’s EA matches IABR[CEA] OR instruction’s EA matches IABR2[CEA]
1 Instruction’s EA matches IABR[CEA] AND instruction’s EA matches IABR2[CEA]
15
DNS
Do not signal. Disable core_iabr and core_iabr2 output
signals
0 Allow signal to toggle on a match
1 Do not toggle signal on match
0
7 8
9 10
1112
13 14 15 16
29 30
31
CMP
0000_0000_0000
CMP2
0000_0000
00
SIG_TYPE
DNS
Reserved
CEA
WBE
BT
RBE
0
29
30
31
F
Freescale Semiconductor, Inc.
n
.