
MOTOROLA
Chapter 9. Core Interface Operation
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9-5
Memory Access Protocol
9.1.3
Optional 32-Bit Data Bus Mode
The G2 core supports an optional 32-bit data bus mode, which differs from the 64-bit data
bus mode only in the byte lanes involved in data transfers and the number of data beats
performed. A data tenure in the 32-bit data bus mode takes one, two, or eight beats
depending on the transfer size and the cache mode for the address. For additional
information, see Section 9.6.1, “32-Bit Data Bus Mode.”
9.1.4
Direct-Store Accesses
The G2 core does not support the extended transfer protocol for accesses to the direct-store
storage space. If SR[T] is set, the memory access is a direct-store access. An attempt to
access to a direct-store segment results in a DSI exception.
9.2
Memory Access Protocol
Figure 9-2 shows that the address and data tenures are distinct from one another and that
both consist of three phases—arbitration, transfer, and termination. Address and data
tenures are independent (indicated in Figure 9-2 by the fact that the data tenure begins
before the address tenure ends), which allows split-bus transactions to be implemented at
the system level in multiprocessor systems. Figure 9-2 shows a data transfer that consists
of a single-beat transfer of as many as 64 bits. Four-beat burst transfers of 32-byte cache
lines require data transfer termination signals for each beat of data.
Figure 9-2. Overlapping Tenures on the Bus for a Single-Beat Transfer
Arbitration
Transfer
Termination
Address Tenure
Arbitration
Single-Beat Transfer
Termination
Data Tenure
Independent Address and Data
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