
MOTOROLA
Chapter 9. Core Interface Operation
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Data Bus Tenure
9.4.5
Memory Coherency—MEI Protocol
The G2 core provides dedicated hardware to provide memory coherency by snooping bus
transactions. The address retry capability enforces the three-state, MEI cache-coherency
protocol (see Figure 9-13).
The global (core_gbl_out) output signal indicates whether the current transaction must be
snooped by other snooping devices on the bus. Address bus masters assert core_gbl_out to
indicate that the current transaction is a global access (that is, an access to memory shared
by more than one device). If core_gbl_in is not asserted for the transaction, that transaction
is not snooped. When other devices detect the core_gbl_in input asserted, they must
respond by snooping the broadcast address.
Normally, core_gbl_out reflects the M-bit value specified for the memory reference in the
corresponding translation descriptor. Note that care must be taken to minimize the number
of pages marked as global, because the retry protocol discussed in the previous
Section 9.4.4, “Data Transfer Termination” is used to enforce coherency and can require
significant bus bandwidth.
When the G2 core is not the address bus master, core_gbl_out is an input. The core snoops
a transaction if core_ts and core_gbl_out are asserted together in the same bus clock cycle
(this is a qualified snooping condition). No snoop update to the core cache occurs if the
snooped transaction is not marked global. This includes invalidation cycles.
When the G2 core detects a qualified snoop condition, the address associated with the
core_ts is compared against the data cache tags. Snooping completes if no hit is detected.
However, if the address hits in the cache, the core reacts according to the MEI protocol
shown in Figure 9-13, assuming the WIM bits are set to write-back, caching-allowed, and
coherency-enforced modes (WIM = 001).
The G2 core on-chip data cache is implemented as a four-way set-associative cache. To
facilitate external monitoring of the internal cache tags, the cache set entry (core_cse[0:1])
signals indicate which cache set is being replaced on read operations. Note that these
signals are valid only for core burst operations; for all other bus operations, core_cse[0:1]
should be ignored.
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