
Index-2
G2 PowerPC Core Reference Manual
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MOTOROLA
C–C
Boundedly undefined, definition, 3-6
BPU, 1-1
BR signal, 8-11, 9-6
Branch folding, 7-2, 7-17
Branch instructions
address calculation, 3-26
branch instructions, 3-26, A-22
condition register logical, 3-27, A-22
system linkage, 3-33, A-23
trap, 3-27, A-23
Branch prediction, 7-1, 7-18
Branch processing unit, 7-4
branch instruction timing, 7-20
execution timing, 7-16
latency, branch instructions, 7-26
overview, 1-9
Branch resolution definition, 7-1
Branch trace enable (BE), 2-7, 11-3, 11-5
Breakpoint
condition, 11-2
enabled, 11-4
exception, 11-2
registers, 11-1
Burst data transfers
32-bit data bus, 9-14
64-bit data bus, 9-14
transfers with data delays, timing, 9-35
Burst transactions, 4-9
Bus arbitration,
see
Data bus
Bus configurations, 9-37, 9-39
Bus interface unit (BIU), 4-2
Bus snooping, 10-2
Byte ordering
considerations, 5-21
default, 3-1, 3-9
Byte-reverse instructions, 3-21, A-20
C
C bit, 6-39
Cache
cache locking
address translation
data cache locking, 4-34
instruction cache locking, 4-39
BAT examples, 4-34
data cache locking
address translation, 4-34
disabling exceptions, 4-35
enabling, 4-34
entire cache locking, 4-37
invalidation, 4-36
invalidation (if locked), 4-38
loading, 4-37
locking, 4-34
MSR bits, 4-35
way-locking, 4-37
disabling exceptions
data cache locking, 4-35
instruction cache locking, 4-40
enabling
data cache, 4-34
instruction cache, 4-38
entire cache locking definition, 4-32
instruction cache locking
address translation, 4-39
disabling, 4-40
enabling, 4-38
entire cache locking, 4-42
invalidating instruction cache (if locked), 4-43
MSR bits, 4-40
preloading instructions, 4-40
way-locking, 4-42
invalidation
data cache, 4-36
data cache (if locked), 4-38
instruction cache (if locked), 4-43
loading
data cache, 4-37
instruction cache preloading, 4-40
MSR bits
disabling exceptions, data cache locking, 4-35
disabling instruction cache locking, 4-40
organization, 4-32
procedures, 4-33
register summary, 4-32
terminology, 4-32
way-locking definition, 4-32
cache miss, 7-13
characteristics, 4-1
instructions, 3-31, 3-35, 4-22, A-23
MEI state definition, 4-16
organization, instruction/data, 4-3-4-8
overview, 1-24
Cache arbitration, 7-10
Cache block push operation, 4-9
Cache block, definition, 4-1
Cache cast-out operation, 4-9
Cache coherency
actions on load operations, 4-19
actions on store operations, 4-19
copy-back operation, 4-12
in single-processor systems, 4-19
MEI protocol, 4-15
out-of-order execution, 4-14
overview, 4-3
protocol, 4-3
reaction to bus operations, 4-20
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