
MOTOROLA
Chapter 11. Debug Features
11-1
Chapter 11
Debug Features
This chapter describes the debug features of the PowerPC architecture with respect to the
G2_LE core. Both the G2 and G2_LE include the trace facility debug feature. However, the
G2_LE core has improved debug capability by enhancing the JTAG/COP interface. The
enhanced debug features are described as follows:
Addition of three breakpoint registers
Inclusions of watchpoint/breakpoint indication signals—core_iabr, core_iabr2,
core_dabr, and core_dabr2
Addition of COP_SVR instruction
New force-single-step operation instruction
11.1 Breakpoint Facilities
The G2_LE core provides enhanced debug facilities—instruction address breakpoint, data
address breakpoint, and program single stepping to enable software debug events. The
existing IABR and single-step functions are facilitated by the new debug features. The
debug facilities consist of a set of debug control registers (DBCR, IBCR), a set of
instruction address breakpoint registers (IABR, IABR2), and a set of data address
breakpoint registers (DABR, DABR2). The basic operation of the DABRs are similar to
that of the MPC750 processor. For information on the MPC750, see the
MPC750 RISC
Microprocessor Family User’s Manual
. These registers are used together to enable various
breakpoint functions.
These registers are accessible to only supervisor-level programs by the
mfspr
and
mtspr
instructions. The SPR address for the registers can be found in Table 3-33 of Chapter 3,
“Instruction Set Model.”
11.1.1 Instruction Address Breakpoint Registers (IABR,
IABR2)
IABR and IABR2 can be used to cause a breakpoint exception if a specified instruction
address is encountered. The IABR and IABR2 control the instruction address breakpoint
exception. IABR[CEA] and IABR2[CEA] hold the effective address to which each
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