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G2 PowerPC Core Reference Manual
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MOTOROLA
Implementation-Specific Information
Asynchronous, maskable—The external, system management interrupt (SMI), and
decrementer interrupts are maskable asynchronous exceptions. When these
exceptions occur, their handling is postponed until the next instruction, and any
exceptions associated with that instruction, completes execution. If there are no
instructions in the execution units, the exception is taken immediately on
determination of the correct restart address (for loading SRR0).
Asynchronous, nonmaskable—There are two nonmaskable asynchronous
exceptions: system reset and the machine check exception. These exceptions may
not be recoverable, or may provide a limited degree of recoverability. All exceptions
report recoverability through MSR[RI].
1.3.4.2
Implementation-Specific Exception Model
As specified by the PowerPC architecture, all exceptions can be described as either precise
or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some of
which are maskable) are caused by events external to the processor’s execution;
synchronous exceptions, which are all handled precisely by the G2 core, are caused by
instructions. A system management interrupt is an implementation-specific exception. The
exception classes are shown in Table 1-3. The exceptions are listed in Table 5-3 in order of
highest to lowest priority.
Although exceptions have other characteristics as well, such as whether they are maskable
or nonmaskable, the distinctions shown in Table 1-3 define categories of exceptions that the
core handles uniquely. Note that Table 1-3 includes no synchronous imprecise instructions.
While the PowerPC architecture supports imprecise handling of floating-point exceptions,
the core implements floating-point exception modes as precise exceptions.
The G2 core exceptions, and conditions that cause them, are listed in Table 1-4.
Table 1-3. Exception Classifications
Synchronous/Asynchronous
Precise/Imprecise
Exception Type
Asynchronous, nonmaskable
Imprecise
Machine check
System reset
Asynchronous, maskable
Precise
External interrupt
Decrementer
System management interrupt
Critical interrupt
Synchronous
Precise
Instruction-caused exceptions
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