
MOTOROLA
Chapter 8. Signal Descriptions
8-1
Chapter 8
Signal Descriptions
This chapter describes the signals of the G2 core that are candidates for being driven as
external device signals. It contains a concise description of the individual signals, showing
behavior when the signal is asserted and negated, which signals are input/output pairs with
output enable signals, and which signals also have high-impedance control signals.
NOTE
A bar over a signal name indicates that the signal is
active-low—for example, core_artry (address retry) and
core_ts (transfer start). Active-low signals are referred to as
asserted (active) when they are low and negated when they are
high. Signals that are not active-low, such as core_ap[0:3]
(address bus parity signals) and core_tt[0:4] (transfer type
signals) are referred to as asserted when they are high and
negated when they are low.
8.1
Signal Groupings
The G2 core 60x bus interface protocol signals are grouped as follows:
Address arbitration signals—The G2 core uses these signals to arbitrate for 60x
address bus mastership.
Address transfer start signals—These signals indicate that a bus master has begun a
transaction on the address bus of the 60x bus.
Address transfer signals—These signals, consisting of the address bus, address
parity, and address parity error signals, are used to transfer the address and to ensure
the integrity of the transfer.
Transfer attribute signals—These signals provide information about the type of
transfer, such as the transfer size and whether the transaction is bursted,
write-through, or cache-inhibited.
Address transfer termination signals—These signals are used to acknowledge the
end of the address phase of the transaction. They also indicate whether a condition
exists that requires the address phase to be repeated.
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