
B-2
G2 PowerPC Core Reference Manual
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MOTOROLA
Revision Changes From Revision 0 to Revision 1
2.1.2.1, 2-11
In Table 2-5 ,“HID0 Bit Functions,” replace the description of bit 1
with the following:
2.1.2.3, 2-14
Replace the first sentence of the first paragraph with the following:
The G2 core implements an additional hardware
implementation-dependent HID2 register, shown in Figure 2-4,
which enables cache way-locking; the G2_LE core also enables true
little-endian mode and the new additional BAT registers.
Replace Figure 2-4,“Hardware Implementation-Dependent Register 2 (HID2)”
with the following:
2.1.2.3, 2-15
2.1.2.3, 2-15
In Table 2-8, “HID2 Bit Descriptions,” replace the description of bit 15 with the
following:
Chapter 4, 4-1
Replace the last sentence of the second paragraph with the following:
It also describes the cache way-locking features provided in the G2
core.
Replace the second paragraph with the following:
Note that the G2 core also provides instruction cache way-locking in
addition to entire instruction cache locking as described in Section
4.12, “Cache Locking.”
Replace the second paragraph with the following:
Note that the G2 core also provides instruction cache way-locking in
addition to entire data cache locking as described in Section 4.12,
“Cache Locking.”
In Figure 4-3, “Double-Word Address Ordering—
Critical-Double-Word-First,” remove ‘G2_LE Core Cache Address’
from the first heading and replace it with the ‘G2 Core Cache
Address.’
4.2.3.3, 4-5
4.3.3.3, 4-7
4.5.2, 4-10
1
—
Reserved
15
—
Reserved
31
27
26
24
23
19
18
14
13
12
4
0
IWLCK[0–2]
0
0
0
0
0
0
0
0
0
0
HBE
DWLCK[0–2]
0
0
0
0
0
0
0
0
3
5
0
0
LET
15
0
0
0
16
Reserved
0
0
F
Freescale Semiconductor, Inc.
n
.