
MOTOROLA
Chapter 11. Debug Features
11-5
Watchpoint Signaling
routine should disable the instruction address breakpoint and set SRR0 to set the MSR[SE]
on the
rfi
. The trace exception is taken after the IABR exception is executed. In any
exception, the value of MSR is saved in SRR0. MSR[SE] is no longer set along with
single-step is disabled. Finally, the trace exception examines the result through a routine
and sets SRR0 to disable MSR[SE] on the
rfi
or to execute the next instruction.
Single-stepping skips
isync
,
sync
,
rfi
,
rfci
,
and
branch instruction
s
because they do not
enter the instruction pipeline. The branch trace may be used for
rfi
,
rfci
,
and
branch
instruction
s.
Also, single-step debugging condition over a
mtmsr
may give unwanted results. Once
MSR is updated, single stepping may be disabled and the G2 core continues executing
instructions without this debugging conditions. Thus, it is recommended to disable and
enable MSR[SE] by using SRR0 within an interrupt. Therefore,
rfi
is responsible for
setting or configuring MSR[SE].
11.2.3 Branch Trace Enabled
When MSR[BE] (branch trace enable) is set, the processor generates a trace exception
(0x00D00) upon the successful completion of a branch instruction. If softstop or hardstop
is enabled, and MSR[SE] is set, the machine stops before the present instruction is retired,
and does not take a trace exception.
11.2.4 Address Matching
On G2 and G2_LE a match occurs when an address equals to an effective address in a
breakpoint register. The G2_LE can match addresses on greater than or equal or less than
as an additional matching condition for IBCR and DBCR.
11.2.5 Combinational Matching
An address match can be signaled after an OR function of the two compared addresses
match or the AND of the two addresses match, depending on the setting of IBCR and
DBCR associated with the enabled breakpoint registers. This feature along with matching
on greater than and less than allows a breakpoint to be set inside or outside a range of two
addresses. The instruction address breakpoints and data address breakpoints always work
independently of each other. For more details, see Section 2.1.2.14.1, “Instruction Address
Breakpoint Control Registers (IBCR)—G2_LE Only” and Section 2.1.2.15.1, “Data
Address Breakpoint Control Registers (DBCR)—G2_LE-Only.”
11.3 Watchpoint Signaling
There is a mechanism to enable address matching but it also disables the signaling of an
exception on a softstop. This allows observing address matching on the watchpoint signals
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n
.