
MOTOROLA
Chapter 6. Memory Management
6-21
Memory Segment Model
6.4
Memory Segment Model
The G2 core adheres to the memory segment model as defined in Chapter 7, “Memory
Management,” in the
Programming Environments Manual
for 32-bit implementations.
Memory in the OEA is divided into 256-Mbyte segments. This segmented memory model
provides a way to map 4-Kbyte pages of effective addresses to 4-Kbyte pages in physical
memory (page address translation), while providing the programming flexibility afforded
by a large virtual address space (52 bits).
The segment/page address translation mechanism may be superseded by the BAT
mechanism described in Section 6.3, “Block Address Translation.” If not, the translation
proceeds in the following two steps:
1. From effective address to the virtual address (which never exists as a specific entity,
but can be considered to be the concatenation of the virtual page number and the byte
offset within a page).
2. From virtual address to physical address.
The following section highlights those areas of the memory segment model defined by the
OEA that are specific to the G2 core.
6.4.1
Page History Recording
Referenced (R) and changed (C) bits reside in each PTE to keep history information about
the page. They are maintained by a combination of the core hardware and the table search
software. The operating system uses this information to determine which areas of memory
to write back to disk when new pages must be allocated in main memory. Referenced and
changed recording is performed only for accesses made with page address translation and
not for translations made with the BAT mechanism or for accesses that correspond to
direct-store interface (T = 1) segments. Furthermore, R and C bits are maintained only for
accesses made while address translation is enabled (MSR[IR] = 1 or MSR[DR] = 1).
In the G2 core, the referenced and changed bits are updated as follows:
For TLB hits, the C bit is updated according to Table 6-7.
For TLB misses, when a table search operation is in progress to locate a PTE, the R
and C bits are updated (set, if required) to reflect the status of the page based on this
access.
Table 6-7 shows that the status of the C bit in the TLB entry (in the case of a TLB hit) is
what causes the processor to update the C bit in the PTE (the R bit is assumed to be set in
the page tables if there is a TLB hit). Therefore, when software clears the R and C bits in
the page tables in memory, it must invalidate the TLB entries associated with the pages
whose referenced and changed bits were cleared.
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