
MOTOROLA
Glossary of Terms and Abbreviations
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Glossary-7
Imprecise exception.
A type of
synchronous exception
that is allowed not
to adhere to the precise exception model (see
Precise exception
). The
PowerPC architecture allows only floating-point exceptions to be
handled imprecisely.
Instruction queue.
A holding place for instructions fetched from the current
instruction stream.
Integer unit.
The functional unit in the G2 responsible for executing all
integer instructions.
In-order.
An aspect of an operation that adheres to a sequential model. An
operation is said to be performed in-order if, at the time that it is
performed, it is known to be required by the sequential execution
model. See
Out-of-order
.
Instruction latency.
The total number of clock cycles necessary to execute
an instruction and make ready the results of that instruction.
Interrupt.
An external signal that causes the G2 to suspend current
execution and take a predefined exception.
K
Key bits.
A set of key bits referred to as Ks and Kp in each segment register
and each BAT register. The key bits determine whether supervisor or
user programs can access a
page
within that
segment
or
block
.
Kill.
An operation that causes a
cache block
to be invalidated without
writing any modified data to memory.
L
Latency.
The number of clock cycles necessary to execute an instruction
and make ready the results of that execution for a subsequent
instruction.
L2 cache.
See
Secondary
cache
.
Least-significant bit (lsb).
The bit of least value in an address, register,
field, data element, or instruction encoding.
Least-significant byte (LSB).
The byte of least value in an address, register,
data element, or instruction encoding.
Little-endian.
A byte-ordering method in memory where the address
n
of a
word corresponds to the
least-significant byte
. In an addressed
memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3
being the
most-significant byte
. See
Big-endian
.
F
Freescale Semiconductor, Inc.
n
.