
MOTOROLA
Chapter 6. Memory Management
6-45
Page Table Search Operation
#
#
#-
r2 is pointer to pteg
r3 is current compare value
.csect
.org
tlbmiss[PR]
vec0+0x1100
tlbDataMiss:
mfspr
addi
mfctr
mfspr
addi
mtctr
lwzu
cmp
bdnzf
bne
l
mtctr
mfspr
mfspr
mtcrf
mtspr
ori
srw
tlbld
stb
rfi
r2, hash1
r1, 0, 8
r0
r3, dCmp
r2, r2, -8
r1
r1, 8(r2)
c0, r1, r3
0, dm1
dataSecHash
r1, +4(r2)
r0
r0, dMiss
r3, srr1
0x80, r3
rpa, r1
r1, r1, 0x100
r1, r1, 8
r0
r1, +6(r2)
# get first pointer
# load 8 for counter
# save counter
# get first compare value
# pre dec the pointer
# load counter
# get next pte
# see if found pte
# dec count br if cmp ne and if count not zero
# if not found set up second hash or exit
# load tlb entry lower-word
# restore counter
# get the miss address for the tlbld
# get the saved cr0 bits
# restore CR0
# set the pte
# set reference bit
# get byte 7 of pte
# load the dtlb
# update page table
# return to executing program
dm0:
dm1:
#+
# Register usage:
#
r0 is saved counter
#
r1 is junk
#
r2 is pointer to pteg
#
r3 is current compare value
#-
dataSecHash:
andi.
bne
mfspr
ori
addi
addi
b
r1, r3, 0x0040
doDSI
r2, hash2
r3, r3, 0x0040
r1, 0, 8
r2, r2, -8
dm0
# see if we have done second hash
# if so, go to DSI exception
# get the second pointer
# change the compare value
# load 8 for counter
# pre dec for update on load
# try second hash
#
#+
# C=0 in dtlb and dtlb miss on store flow
# Entry:
#
Vec = 1200
#
srr0
-> address of store that caused the exception
#
srr1
-> 0:3=cr0 4=lru way bit 5=1 16:31 = saved MSR
#
msr<tgpr> -> 1
F
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