
MOTOROLA
Glossary of Terms and Abbreviations
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Glossary-1
Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this
book. Some of the terms and definitions included in the glossary are reprinted from IEEE
Standard 754-1985,
IEEE Standard for Binary Floating-Point Arithmetic
, copyright 1985
by the Institute of Electrical and Electronics Engineers, Inc. with the permission of the
IEEE.
A
Architecture.
A detailed specification of requirements for a processor or
computer system. It does not specify details of how the processor or
computer system must be implemented; instead it provides a
template for a family of compatible
implementations
.
Asynchronous exception.
Exceptions
that are caused by events external to
the processor’s execution. In this document, the term
asynchronous
exception
is used interchangeably with the word
interrupt
.
Atomic access.
A bus access that attempts to be part of a read-write
operation to the same address uninterrupted by any other access to
that address (the term refers to the fact that the transactions are
indivisible). The PowerPC architecture implements
atomic
accesses
through the
lwarx
/
stwcx.
instruction pair.
B
BAT (block address translation) mechanism.
A software-controlled array
that stores the available block address translations on-chip.
Beat.
A single state on the G2 bus interface that may extend across multiple
data
beats
.
Biased exponent.
An
exponent
whose range of values is shifted by a
constant (bias). Typically a bias is provided to allow a range of
positive values to express a range that includes both positive and
negative values.
F
Freescale Semiconductor, Inc.
n
.