
MOTOROLA
Chapter 8. Signal Descriptions
8-21
Signal Descriptions
8.3.4.1.2
Transfer Type Out (core_tt_out[0:4])
Following are the state meaning and timing comments for core_tt_out[0:4].
State Meaning
Asserted/Negated—Indicates the type of transfer in progress.
Timing Comments
Assertion/Negation/High Impedance—The same as
core_a_out[0:31].
Table 8-6 describes the transfer type encodings for the G2 core as a bus master.
Read-with-no-intent-to-cache
Single-beat read or burst
0
1
0
1
1
Clean
Reserved
—
0
1
1
1
1
N/A
Reserved
—
1
X
X
1
1
N/A
Table 8-6. Transfer Type Encoding for the G2 Core as a Bus Master
G2 Core Bus
Master
Transaction
Transaction
Source
core_tt_out
x
60x Bus
Specification
Command
Transaction
Type
tt0
tt1
tt2
tt3
tt4
N/A
N/A
0
0
0
0
0
Clean block
Address only
N/A
N/A
0
0
1
0
0
Flush block
Address only
N/A
N/A
0
1
0
0
0
sync
Address only
Address only
dcbz
0
1
1
0
0
Kill block
Address only
N/A
N/A
1
0
0
0
0
eieio
Address only
Single-beat write
(nongbl)
ecowx
1
0
1
0
0
External control word
write
Single-beat
write
N/A
N/A
1
1
0
0
0
TLB invalidate
Address only
Single-beat read
(nongbl)
eciwx
1
1
1
0
0
External control word
read
Single-beat read
N/A
N/A
0
0
0
0
1
lwarx
Reservation set
Address only
N/A
N/A
0
0
1
0
1
Reserved
—
N/A
N/A
0
1
0
0
1
tlbsync
Address only
N/A
N/A
0
1
1
0
1
icbi
Address only
N/A
N/A
1
X
X
0
1
Reserved
—
Single-beat write
Caching-inhibited
or write-through
store
0
0
0
1
0
Write-with-flush
Single-beat
write or burst
Burst (nongbl)
Cast-out, or snoop
copy back
0
0
1
1
0
Write-with-kill
Single-beat
write or burst
Table 8-5. G2 Core Snoop Hit Response (continued)
60x Bus Specification
Command
Transaction Type
core_tt_in
x
G2 Core as
Snooper;
Action on Hit
tt0
tt1
tt2
tt3
tt4
F
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