
9-16
G2 PowerPC Core Reference Manual
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MOTOROLA
Address Bus Tenure
Due to the performance degradations associated with misaligned memory operations, they
are best avoided. Address translation logic can also generate substantial exception overhead
when the load/store multiple and load/store string instructions access misaligned data,
another reason to avoid using these instructions. It is strongly recommended that software
attempt to align code and data where possible.
9.3.2.5
Effect of Alignment in Data Transfers (32-Bit Bus)
The aligned data transfer cases for 32-bit data bus mode are shown in Table 9-7. All of the
transfers require a single data beat (if caching-inhibited or write-through) except for
double-word cases which require two data beats. The double-word case is only generated
by the core for load or store double operations to/from the floating-point GPRs. All
caching-inhibited instruction fetches are performed as word operations.
Table 9-6. Misaligned Data Transfers (4-Byte Examples)
Transfer Size
(4 Bytes)
tsiz[0:2]
core_a_out
[29:31]
Data Bus Byte Lanes
0
1
2
3
4
5
6
7
Aligned
1 0 0
0 0 0
A
A
A
A
—
—
—
—
Misaligned:
First access
0 1 1
0 0 1
A
A
A
—
—
—
—
Second access
0 0 1
1 0 0
—
—
—
—
A
—
—
—
Misaligned:
First access
0 1 0
0 1 0
—
—
A
A
—
—
—
—
Second access
0 1 0
1 0 0
—
—
—
—
A
A
—
—
Misaligned:
First access
0 0 1
0 1 1
—
—
—
A
—
—
—
—
Second access
0 1 1
1 0 0
—
—
—
—
A
A
A
—
Aligned
1 0 0
1 0 0
—
—
—
—
A
A
A
A
Misaligned:
First access
0 1 1
1 0 1
—
—
—
—
—
A
A
A
Second access
0 0 1
0 0 0
A
—
—
—
—
—
—
—
Misaligned:
First access
0 1 0
1 1 0
—
—
—
—
—
—
A
A
Second access
0 1 0
0 0 0
A
A
—
—
—
—
—
—
Misaligned:
First access
0 0 1
1 1 1
—
—
—
—
—
—
—
A
Second access
0 1 1
0 0 0
A
A
A
—
—
—
—
—
Notes
:
A:
—
:
Byte lane not used.
Byte lane used.
F
Freescale Semiconductor, Inc.
n
.