
8-20
G2 PowerPC Core Reference Manual
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MOTOROLA
Signal Descriptions
8.3.4.1.1
Transfer Type In (core_tt_in[0:4])
Following are the state meaning and timing comments for core_tt_in[0:4].
State Meaning
Asserted/Negated—Indicates the type of transfer in progress (see
Table 8-5).
Timing Comments
Assertion/Negation—The same as core_a_in[0:31].
Table 8-5 describes the 60x bus specification transfer encodings and the G2 core bus snoop
response on an address hit.
Table 8-5. G2 Core Snoop Hit Response
60x Bus Specification
Command
Transaction Type
core_tt_in
x
G2 Core as
Snooper;
Action on Hit
tt0
tt1
tt2
tt3
tt4
Clean block
Address only
0
0
0
0
0
N/A
Flush block
Address only
0
0
1
0
0
N/A
sync
Address only
0
1
0
0
0
N/A
Kill block
Address only
0
1
1
0
0
Kill, cancel
reservation
eieio
Address only
1
0
0
0
0
N/A
External control word write
Single-beat write
1
0
1
0
0
N/A
TLB invalidate
Address only
1
1
0
0
0
N/A
External control word read
Single-beat read
1
1
1
0
0
N/A
lwarx reservation set
Address only
0
0
0
0
1
N/A
Reserved
—
0
0
1
0
1
N/A
tlbsync
Address only
0
1
0
0
1
N/A
icbi
Address only
0
1
1
0
1
N/A
Reserved
—
1
X
X
0
1
N/A
Write-with-flush
Single-beat write or burst
0
0
0
1
0
Flush, cancel
reservation
Write-with-kill
Single-beat write or burst
0
0
1
1
0
Kill, cancel
reservation
Read
Single-beat read or burst
0
1
0
1
0
Clean or flush
Read-with-intent-to-modify
Burst
0
1
1
1
0
Flush
Write-with-flush-atomic
Single-beat write
1
0
0
1
0
Flush, cancel
reservation
Reserved
N/A
1
0
1
1
0
N/A
Read-atomic
Single-beat read or burst
1
1
0
1
0
Clean or flush
Read-with-intent-to modify-
atomic
Burst
1
1
1
1
0
Flush
Reserved
—
0
0
0
1
1
N/A
Reserved
—
0
0
1
1
1
N/A
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