
11-2
G2 PowerPC Core Reference Manual
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MOTOROLA
Breakpoint Facilities
instruction’s address is compared. The exception is enabled by setting IABR[BE]. The
exception is taken when there is an instruction address breakpoint match on the next
instruction to complete. The instruction tagged with the match cannot complete before the
instruction address breakpoint exception (0x01300) is taken. The address of the instruction
that matches the breakpoint condition is stored in SRR0. The tagged instruction retires after
returning from the exception (
rfi
or
rfci
). The results are then committed to the destination
registers and address.
If the IABR or IABR2 values are set to any exception vector range, an unrecoverable state
occurs. The IABR or IABR2 values should never be set to match within the instruction
address breakpoint exception handler. Failure to prohibit a breakpoint within any handler
may result in an indeterminate or unrecoverable processor state. See Section 2.1.2.14,
“Instruction Address Breakpoint Registers (IABR and IABR2),” for bit descriptions.
11.1.2 Instructional Address Control Register (IBCR)
IBCR is a supervisor-level SPR. It controls the compare and match type conditions for
IABR and IABR2. Note that IABR and IABR2 must be enabled before the effects of IBCR
are realized. See Section 2.1.2.14.1, “Instruction Address Breakpoint Control Registers
(IBCR)—G2_LE Only,” for bit descriptions.
11.1.3 Data Address Breakpoint Registers (DABR, DABR2)
The DABR and DABR2 registers are used to cause a breakpoint exception if the specified
address is encountered. DABR[CEA] and DABR2[CEA] hold an effective address to
which each address of data access is compared. The breakpoint translation matches when a
data address breakpoint matches (MSR[DR] = DABR[BT]). The data address write and
data address read exceptions are enabled by setting DABR[WBE,RBE] and
DABR2[WBE,RBE]. The data tagged with the match does not complete before the
breakpoint exception is taken.
The DSI exception (0x00300) occurs when there is a data address breakpoint match. The
DSI exception is taken before the load or store instruction is executed. When the exception
is taken, DAR is set to the data address that causes the breakpoint and DSISR[DABR] is
set to indicate a data address breakpoint. The address of the instruction associated with the
breakpoint condition is stored in SRR0. The instruction retires after returning from the DSI
exception, and all registers and memory accesses are committed to memory.
An unrecoverable state occurs whenever DABR or DABR2 values are set to an exception
vector. These values must not be set to match within the DSI exception handler or the
G2_LE core may enter an indeterminate or unrecoverable processor core state.
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n
.