
3-4
G2 PowerPC Core Reference Manual
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MOTOROLA
Operand Conventions
architecture provides for hardware to implement a floating-point system as defined in
ANSI/IEEE Standard 754-1985,
IEEE Standard for Binary Floating Point Arithmetic
. For
detailed information about the floating-point execution model, refer to Chapter 3, “Operand
Conventions,” in the
Programming Environments Manual
.
The IEEE 754 standard includes 64- and 32-bit arithmetic. The standard requires that
single-precision arithmetic be provided for single-precision operands. The standard permits
double-precision arithmetic instructions to have either (or both) single-precision or
double-precision operands, but states that single-precision arithmetic instructions should
not accept double-precision operands.
The UISA follows these guidelines:
Double-precision arithmetic instructions may have single-precision operands but
always produce double-precision results.
Single-precision arithmetic instructions require all operands to be single-precision
and always produce single-precision results.
For arithmetic instructions, conversions from double- to single-precision must be done
explicitly by software, while conversions from single- to double-precision are done
implicitly.
All PowerPC implementations provide the equivalent of the following execution models to
ensure that identical results are obtained. The definition of the arithmetic instructions for
infinities, denormalized numbers, and NaNs follow conventions described in the following
sections.
Although the double-precision format specifies an 11-bit exponent, exponent arithmetic
uses two additional bit positions to avoid potential transient overflow conditions. An extra
bit is required when denormalized double-precision numbers are prenormalized. A second
bit is required to permit computation of the adjusted exponent value in the following
examples when the corresponding exception enable bit is one:
Underflow during multiplication using a denormalized factor
Overflow during division using a denormalized divisor
3.1.5
Effect of Operand Placement on Performance
The VEA states that the placement (location and alignment) of operands in memory affect
the relative performance of memory accesses. The best performance is guaranteed if
memory operands are aligned on natural boundaries. To obtain the best performance from
the core, the programmer should assume the performance model described in Chapter 3,
“Operand Conventions,” in the
Programming Environments Manual
.
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.