
MT9071
Preliminary Information
88
18.2 T1 & E1 Interrupt Servicing Methods
There are three common methods for identifying the source of the interrupt. The Polling Method is the simplest
but uses the most processor time. The Vector Method requires a two step process, but uses the least amount
of processor time. The Timer Polling Method interrupts the processor once a second using an internal timer.
18.2.1
T1 & E1 Polling Method
The IRQ pin goes low.
1. Read all 16 interrupt status registers. The set bits in these registers identify the source of the interrupt. As
each register is read, it is cleared (all bits set to 0). When all registers are clear, the interrupt is cleared (the
IRQ pin returns to logic high) and all sources of the interrupt are identified. Service the interrupt as each
register is read, or all at once, after all registers are read and the interrupt is cleared.
18.2.2
T1 & E1 Vector Method
The IRQ pin goes low.
1. Read the interrupt vector. This vector identifies which of the 16 (or which combination of 16) interrupt status
registers has a set bit.
2. Read the interrupt status register(s) identified in step 1. The set bits in these registers identify the source of
the interrupt. Note that if multiple transceivers (i.e. transceiver 1 and 3), or multiple conditions caused the
interrupt, more than one register may need to be read. As each register is read, it is cleared (all bits set to 0).
When all interrupt status registers are cleared, the interrupt vector goes to zero and the IRQ pin returns to logic
high. Service the interrupt as each register is read, or all at once, after all registers are read and the interrupt is
cleared.
18.2.3
T1 & E1 Timer Polling Method
The IRQ pin goes low.
1. The one second timer caused the interrupt as this is the only unmasked interrupt bit, read the timer interrupt
status register to clear the source of the interrupt.
2. Read the desired latched status registers (all the interrupt status registers are all masked except for the
timer). Service the interrupt as each register is read, or all at once, after all registers are read.
18.2.4
T1 & E1 Hints
In some applications, a logic low at the IRQ pin lasting the full duration of the interrupt service routine may be
undesirable. In these cases, immediately following the interrupt, set the control register bit SPND low until the
interrupt service routine is finished.