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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 119/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
119
12
T2OP
(0)
T2o Polarity.
This is normally set to zero. If one, the T2o pin will output a 2.048MHz clock whose
rising edge is in the center of the transmitted PCM30 bit cell at the TPOS and TNEG transmit pins.
This clock is equivalent to the internal ST-BUS C2 clock. If zero, the T2o pin will output a
2.048MHz clock whose falling edge is in the center of the transmitted PCM30 bit cell at the TPOS
and TNEG transmit pins. This clock is equivalent to the internal ST-BUS C2 clock.
Transmit Multiframe Enable.
If one, the TxMF pin will be enabled. If zero, the TxMF pin will be
disabled. See the TxMF pin description.
Transmit 8 KHz Enable.
This is normally set to zero but may be used in conjunction with the
auxiliary signals, see Section 3.6 Auxiliary Output Signals. If one, the pin RxMF (AUX pin, see
Section 3.6 Auxiliary Output Signals) transmits a positive 8 KHz frame pulse synchronous with the
serial data stream transmit on TTIP/TRNG. If zero, the pin RxMF transmits a negative frame pulse
synchronous with the multiframe boundary of data coming out of DSTo.
Suspend Interrupts.
If zero, the selected tranceivers contribution to the IRQ pin output will be a
high impedance state, but all interrupt and latched status registers will continue to be updated. If
one, the selected tranceivers contribution to the IRQ output will be normal operation.
Interrupt Acknowledge.
If zero, all interrupt and latched status registers are cleared and
consequently, the selected tranceivers contribution to the IRQ pin output will be a high impedance
state. If one, all interrupt and latched status registers operate normally, and the selected
tranceivers contribution to the IRQ output will be normal operation.
Clock Edge.
This is normally set to zero. If one, the NRZ data at the framer-LIU interface (RPOS/
RNEG and TPOS/TNEG) is sampled on the rising edge of the extracted clock and transmitted on
the falling edge of the transmitted clock. If zero, the opposite edges are used. This selection is
only applicable in NRZ mode.
HDB3 (High Density Bipolar 3) TX encoding.
If zero, HDB3 encoding is enabled in the transmit
direction. If one, AMI (Alternate Mark Inversion) signal without HDB3 encoding is enabled in the
transmit direction.
Receive Basic Frame Enable.
If one, the RxBF pin operates normally. If zero, the RxBF pin is
low.
Receive DSTo All Ones.
If one, the DSTo pin operates normally. If zero, all timeslots (0-31) of
DSTo are set to one.
Receive CSTo All Ones.
If one, the CSTo pin operates normally. If zero, all timeslots (0-31) of
CSTo are set to one.
Output CSTo Enable.
If one, the CSTo pin operates normally. If zero, CSTo will be at high
impedance. Note in 8 Meg mode all CSTOE for all framers have to be 0 to obtain high impedance.
Output DSTo Enable.
If one, the DSTo pin operates normally. If zero, DSTo will be at high
impedance.
Multiframe Select.
This is normally set to zero but may be used in conjunction with the auxiliary
signals, see Section 3.6 Auxiliary Output SIgnals. This bit determines which receive multiframe
signal (CRC-4 or signaling) the frame pulse at the RxMF pin is aligned with. If zero, the frame
pulse at the RxMF pin is aligned with the receive channel associated signaling (CAS) multiframe;
if one, the receive CRC-4 multiframe.
Table 83 - E1 Interrupts and I/O Control - R/W Address Y02
11
TXMFE
(0)
TX8KE
(0)
10
9
SPND
(0)
8
INTA
(0)
7
CLKE
(0)
6
THDB3
(0)
5
RXBFE
(0)
RXDO
(0)
RXCO
(0)
CSTOE
(0)
DSTOE
(0)
MFSEL
(0)
4
3
2
1
0
Bit
Name
Functional Description
15-7 (#### #### #) Not Used
6
L32Z
(0)
Digital Loss of Signal Selection
. If one, the threshold for digital loss of signal is 32
successive zeros. If zero, the threshold is set to 192 successive zeros. See the LOSS bit
detailed in Table 104 - T1 Synchronization and Alarm Status - R Address Y10.
Table 84 - T1 Transmit Error Control - R/W Address Y03
Bit
Name
Functional Description
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90710 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:High-Speed Isochronous Multiplexer |
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| MT9072AB | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Octal T1/E1/J1 Framer |
| MT9072AV | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 256BGA - Trays |
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