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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 151/217頁(yè) |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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Preliminary Information
MT9071
151
9
VEIL
(0)
Bipolar Violation Counter Indication Latch.
When the corresponding counter (T1 Bipolar
Violation Counter - R/W Address Y18) is incremented by one, this status bit is latched to one. It
is cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R
Address Y35 is read.
PRBS Error Counter Indication Latch.
When the corresponding counter (T1 PRBS CRC
Multiframe and PRBS Error Counter - R/W Address Y15) is incremented by one, this status bit
is latched to one. It is cleared when either this register, or the T1 Receive Line and Timer
Interrupt Status - R Address Y35 is read.
Pulse Density Violation Latch.
When the PDV status bit (T1 Synchronization and Alarm
Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It is cleared
when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is
read.
Line Loopback Enable Detect Latch.
When the LLED status bit (T1 Synchronization and
Alarm Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address
Y35 is read.
Line Loopback Disable Detect Latch.
When the LLDD status bit (T1 Synchronization and
Alarm Status - R Address Y10) toggles from zero to one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address
Y35 is read.
Bit Oriented Message Latch.
When the RXBOM status bit (T1 Receive Bit Oriented
Message - R Address Y12) toggles from zero to one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address
Y35 is read.
Bit Oriented Message Match Latch.
When the RXBOMM status bit (T1 Receive Bit Oriented
Message - R Address Y12) toggles from zero to one, this status bit is latched to one. It is
cleared when either this register, or the T1 Receive Line and Timer Interrupt Status - R Address
Y35 is read.
Channel Associated Signaling Received Latch.
When any of the 24 receive CAS (i.e.
ABCD) bits in the T1 Receive CAS Data Registers - R Address Y70-Y87 change state, this
status bit is latched to one. This bit is set on a basic frame (FPb) basis. It is cleared when either
this register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is read.
One Second Timer Status Latch.
When the ONESEC status bit (T1 Timer Status - R Address
Y11) toggles from zero to one, this status bit is latched to one. It is cleared when either this
register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is read.
Two Second Timer Status Latch.
When the TWOSEC status bit (T1 Timer Status - R Address
Y11) toggles from zero to one, this status bit is latched to one. It is cleared when either this
register, or the T1 Receive Line and Timer Interrupt Status - R Address Y35 is read.
Table 134 - T1 Receive Line Status and Timer Latch - R Address Y25
8
PEIL
(0)
7
PDVL
(0)
6
LLEDL
(0)
5
LLDDL
(0)
4
BOML
(0)
3
BOMML
(0)
2
CASRL
(0)
1
ONESECL
(0)
0
TWOSECL
(0)
Bit
Name
Functional Description
15
14
(0)
Not Used
Loss of Sync Counter Overflow Latch.
When the corresponding counter (E1 Loss of Basic
Frame Sync Counter - R/W Address Y16) overflows to 0, this status bit is latched to one. It is
cleared when either this register, or the E1 Counter Interrupt Status - R Address Y35 is read.
Frame Alignment Signal (FAS) Error Counter Overflow Latch.
When the corresponding
counter (E1 FAS Bit Error Counter & FAS Error Counter - R/W Address Y1A) overflows to 0,
this status bit is latched to one. It is cleared when either this register, or the E1 Counter
Interrupt Status - R Address Y35 is read.
Table 135 - E1 Counter Latched Status - R Address Y25
SLOL
13
FEOL
Bit
Name
Functional Description
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