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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁(yè)數(shù)： | 164/217頁(yè) |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
164
2
CASRI
(0)
Signaling Interrupt Status.
This bit is one when the corresponding CASRL bit in the T1 Receive
Line Status and Timer Latch - R Address Y25 is set, and the corresponding CASRM bit in the T1
Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when
either this register, or the latched status register is read.
One Second Interrupt Status.
This bit is one when the corresponding ONESECL bit in the T1
Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding ONESECM
bit in the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
Two Second Interrupt Status.
This bit is one when the corresponding TWOSECL bit in the T1
Receive Line Status and Timer Latch - R Address Y25 is set, and the corresponding TWOSECM
bit in the T1 Receive Line and Timer Interrupt Mask - R/W Address Y45 is unmasked. This bit is
cleared when either this register, or the latched status register is read.
Table 151 - T1 Receive Line and Timer Interrupt Status - R Address Y35
1
ONESE
CI
(0)
0
TWOSE
CI
(0)
Bit
Name
Functional Description
15
14
(0)
SLOI
(0)
Not Used
Loss of Sync Counter Overflow Interrupt.
This bit is one when the corresponding SLOL bit in
the E1 Counter Latched Status - R Address Y25 is set, and the corresponding SLOM bit in the
E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Frame Alignment Signal (FAS) Error Counter Overflow Interrupt.
This bit is one when the
corresponding FEOL bit in the E1 Counter Latched Status - R Address Y25 is set, and the
corresponding FEOM bit in the E1 Counter Interrupt Mask - R/W Address Y45 is unmasked.
This bit is cleared when either this register, or the latched status register is read.
Frame Alignment Signal (FAS) Error Counter Indication Interrupt.
This bit is one when the
corresponding FEIL bit in the E1 Counter Latched Status - R Address Y25 is set, and the
corresponding FEIM bit in the E1 Counter Interrupt Mask - R/W Address Y45 is unmasked.
This bit is cleared when either this register, or the latched status register is read.
Frame Alignment Signal (FAS) Bit Error Counter Overflow Interrupt.
This bit is one when
the corresponding BEOL bit in the E1 Counter Latched Status - R Address Y25 is set, and the
corresponding BEOM bit in the E1 Counter Interrupt Mask - R/W Address Y45 is unmasked.
This bit is cleared when either this register, or the latched status register is read.
Frame Alignment Signal (FAS) Bit Error Counter Indication Interrupt.
This bit is one when
the corresponding BEIL bit in the E1 Counter Latched Status - R Address Y25 is set, and the
corresponding BEIM bit in the E1 Counter Interrupt Mask - R/W Address Y45 is unmasked.
This bit is cleared when either this register, or the latched status register is read.
CRC-4 Error Counter Overflow Interrupt.
This bit is one when the corresponding CEOL bit in
the E1 Counter Latched Status - R Address Y25 is set, and the corresponding CEOM bit in the
E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
CRC-4 Error Counter Indication Interrupt.
This bit is one when the corresponding CEIL bit in
the E1 Counter Latched Status - R Address Y25 is set, and the corresponding CEIM bit in the
E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Bipolar Violation Error Counter Overflow Interrupt.
This bit is one when the corresponding
VEOL bit in the E1 Counter Latched Status - R Address Y25 is set, and the corresponding
VEOM bit in the E1 Counter Interrupt Mask - R/W Address Y45 is unmasked. This bit is cleared
when either this register, or the latched status register is read.
Table 152 - E1 Counter Interrupt Status - R Address Y35
13
FEOI
(0)
12
FEII
(0)
11
BEOI
(0)
10
BEII
(0)
9
CEOI
(0)
8
CEII
(0)
7
VEOI
(0)
Bit
Name
Functional Description
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