
MT9071
Preliminary Information
58
Test Data Output (TDO) -
Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO
is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the
TDO driver is set to a high impedance state.
Test Reset (TRST) -
Reset the JTAG scan structure.This pin is internally pulled up to device V
DD
.
8.2
Test Access Port (TAP) Controller
The TAP Controller generates clock and control signals for the Instruction Register (IR) and the Test Data
Registers (TDR’s). The TAP Controller operates synchronously with TCK input clock and responds to the TMS
input signal to generate control signals which shift, capture, or update data through either the IR or the TDR’s.
8.3
Instruction Register
The Instruction Register (IR) is a 3-bit register which allows one of four test instructions to be shifted into the
device. Test instructions are serially loaded into the IR from the TDI pin by the TAP Controller (see Table 14 -
JTAG Instruction Register). These test instructions provided by the MT9071 are in accordance with the IEEE
1149.1 standard.
8.4
Test Data Registers
As specified in IEEE 1149.1, the JTAG Interface must contain as a minimum the boundary scan register and
the bypass register. The device identification register although optional, is also included in the MT9071.
8.4.1
Identification Register
This is a 32 bit register (see Table 15 - JTAG MT9071 Identification Register). Note that the marketing revision
is not the same as the silicon revision which is not supplied.
MSB LSB
Instruction
Name
Functional Description
0
0
0
EXTEST
This instruction isolates the tranceiver logic (on chip logic) from the input and
output pins. The signal states at the output pins is determined by the values
programmed (earlier) in the Boundary Scan Register. This instruction allows
testing of board level interconnects (i.e. open, stuck at, bridge).
This instruction performs two functions. On the rising edge of TCK, the SAMPLE
instruction is performed. With this instruction, the signal states at the input and
output pins is loaded into the Boundary Scan Register. On the falling edge of
TCK, the PRELOAD instruction is performed. With this instruction, the signal
states at the output pins is determined by the values programmed (earlier) in the
Boundary Scan Register.
This instruction forces the value of the 32 bit MT9071 Identification Register into
the Instruction Registers parallel output latches. This is the default instruction
loaded after a JTAG reset.
This instruction connects the Bypass Register between the TDI and TDO pins.
0
1
0
SAMPLE/
PRELOAD
0
0
1
IDCODE
1
1
1
BYPASS
Note 1. The following optional JTAG instructions are not supported, INTEST, RUNBIST and USERCODE.
Table 14 - JTAG Instruction Register