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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 168/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
168
10
PEOM
(0)
PRBS Error Counter Overflow Mask.
This is the mask bit for the corresponding PEOI bit in
the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Multiframe Counter Overflow Mask.
This is the mask bit for the corresponding PCOI bit in the
T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt bit
will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Multiframes Out Of Sync Overflow Mask.
This is the mask bit for the corresponding MFOI bit
in the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Terminal Frame Synchronization Mask.
This is the mask bit for the corresponding TFSYNI
bit in the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Multiframe Synchronization Mask.
This is the mask bit for the corresponding MFSYNI bit in
the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Framing Bit Error Mask.
This is the mask bit for the corresponding BEII bit in the T1 Receive
and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
Change of Frame Alignment Counter Indication Mask.
This is the mask bit for the
corresponding CFII bit in the T1 Receive and Sync Interrupt Status - R Address Y34. If this
mask bit is one, the interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will
function normally.
Severely Errored Frame Mask.
This is the mask bit for the corresponding SEFI bit in the T1
Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Alarm Indication Signal Mask.
This is the mask bit for the corresponding AISI bit in the T1
Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
CRC-6 Error Counter Indication Mask.
This is the mask bit for the corresponding CEII bit in
the T1 Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Digital Loss of Signal Mask.
This is the mask bit for the corresponding LOSI bit in the T1
Receive and Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Table 156 - T1 Receive and Sync Interrupt Mask - R/W Address Y44
9
PCOM
(0)
8
MFOM
(0)
7
TFSYNM
(0)
6
MFSYNM
(0)
5
BEIM
(0)
4
CFIM
(0)
3
SEFM
(0)
2
AISM
(0)
1
CEIM
(0)
0
LOSM
(0)
Bit
Name
Functional Description
15
14
(0)
Not Used
Remote CRC-4 and RAI Mask.
This is the mask bit for the corresponding RCRCRI bit in the
E1 Sync Interrupt Status - R Address Y34. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
Receive Slip Mask.
This is the mask bit for the corresponding RSLPI bit in the E1 Sync
Interrupt Status - R Address Y34. If this mask bit is one, the interrupt bit will remain inactive. If
this mask bit is zero, the interrupt bit will function normally.
Receive Y-bit Mask.
This is the mask bit for the corresponding YI bit in the E1 Sync Interrupt
Status - R Address Y34. If this mask bit is one, the interrupt bit will remain inactive. If this mask
bit is zero, the interrupt bit will function normally.
Table 157 - E1 Sync Interrupt Mask - R/W Address Y44
RCRCRM
(0)
13
RSLPM
(0)
12
YM
(0)
Bit
Name
Functional Description
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