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參數(shù)資料
| 型號： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調節(jié)器（集成四個獨立幀調節(jié)器）） |
| 文件頁數(shù)： | 166/217頁 |
| 文件大?。?/td> | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
166
Bit
Name
Functional Description
15
14
(0)
Not Used
Sa5 Value Bit Interrupt.
This bit is one when the corresponding Sa5VL bit in the E1 National
Latched Status - R Address Y26 is set, and the corresponding Sa5VM bit in the E1 National
Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either this register, or
the latched status register is read.
Sa6 Value Bits 3-0 Interrupt.
This bit is one when the corresponding Sa6V*L bit in the E1
National Latched Status - R Address Y26 is set, and the corresponding Sa6V*M bit in the E1
National Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Sa5VI
(0)
13
12
11
10
Sa6V3I
Sa6V2I
Sa6V1I
Sa6V0I
(0000)
Sa6N8I
(0)
9
Eight Consecutive Sa6 Nibbles Interrupt.
This bit is one when the corresponding Sa6N8L bit
in the E1 National Latched Status - R Address Y26 is set, and the corresponding Sa6N8M bit in
the E1 National Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either
this register, or the latched status register is read.
Sa6 Nibble Change Interrupt.
This bit is one when the corresponding Sa6NL bit in the E1
National Latched Status - R Address Y26 is set, and the corresponding Sa6NM bit in the E1
National Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Sa Nibble Change Interrupt.
This bit is one when the corresponding SaNL bit in the E1
National Latched Status - R Address Y26 is set, and the corresponding SaNM bit in the E1
National Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either this
register, or the latched status register is read.
Sa5 Bit Change Interrupt.
This bit is one when the corresponding Sa5TL bit in the E1 National
Latched Status - R Address Y26 is set, and the corresponding Sa5TM bit in the E1 National
Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either this register, or
the latched status register is read.
Sa Bit Change Interrupt.
This bit is one when the corresponding SaTL bit in the E1 National
Latched Status - R Address Y26 is set, and the corresponding SaTM bit in the E1 National
Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either this register, or
the latched status register is read.
Receive Channel Associated Signaling (CAS) Change Interrupt.
This bit is one when the
corresponding CASRL bit in the E1 National Latched Status - R Address Y26 is set, and the
corresponding CASRM bit in the E1 National Interrupt Mask - R/W Address Y46 is unmasked.
This bit is cleared when either this register, or the latched status register is read.
CRC-4 Alignment 2ms Timer Interrupt.
This bit is one when the corresponding CALNL bit in
the E1 National Latched Status - R Address Y26 is set, and the corresponding CALNM bit in
the E1 National Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either
this register, or the latched status register is read.
Timer 2 Interrupt.
This bit is one when the corresponding T2L bit in the E1 National Latched
Status - R Address Y26 is set, and the corresponding T2M bit in the E1 National Interrupt Mask
- R/W Address Y46 is unmasked. This bit is cleared when either this register, or the latched
status register is read.
Timer 1 Interrupt.
This bit is one when the corresponding T1L bit in the E1 National Latched
Status - R Address Y26 is set, and the corresponding T1M bit in the E1 National Interrupt Mask
- R/W Address Y46 is unmasked. This bit is cleared when either this register, or the latched
status register is read.
One Second Timer Status Interrupt.
This bit is one when the corresponding ONESECL bit in
the E1 National Latched Status - R Address Y26 is set, and the corresponding ONESECM bit in
the E1 National Interrupt Mask - R/W Address Y46 is unmasked. This bit is cleared when either
this register, or the latched status register is read.
Table 154 - E1 National Interrupt Status - R Address Y36
8
Sa6NI
(0)
7
SaNI
(0)
6
Sa5TI
(0)
5
SaTI
(0)
4
CASRI
(0)
3
CALNI
(0)
2
T2I
(0)
1
T1I
(0)
0
ONESEC
I
(0)
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