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參數(shù)資料
| 型號(hào)： | MT9071 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad T1/E1/J1 Transceiver(多端口 T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）) |
| 中文描述： | 四T1/E1/J1收發(fā)器（多端口的T1/E1/J1幀調(diào)節(jié)器（集成四個(gè)獨(dú)立幀調(diào)節(jié)器）） |
| 文件頁數(shù)： | 170/217頁 |
| 文件大小： | 686K |
| 代理商： | MT9071 |
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MT9071
Preliminary Information
170
Bit
Name
Functional Description
15
D4YM
(0)
D4 Yellow Mask.
This is the mask bit for the corresponding D4YI bit in the T1 Receive Line
and Timer Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
D4 Y48 Mask.
This is the mask bit for the corresponding D4Y48I bit in the T1 Receive Line and
Timer Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
Secondary Yellow Mask.
This is the mask bit for the corresponding SECYI bit in the T1
Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
ESF Yellow Mask.
This is the mask bit for the corresponding ESFYI bit in the T1 Receive Line
and Timer Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will remain
inactive. If this mask bit is zero, the interrupt bit will function normally.
T1DM Yellow Mask.
This is the mask bit for the corresponding T1DMYI bit in the T1 Receive
Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the interrupt bit will
remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Not Used
Bipolar Violation Counter Indication Mask.
This is the mask bit for the corresponding VEII
bit in the T1 Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one,
the interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function
normally.
PRBS Error Counter Indication Mask.
This is the mask bit for the corresponding PEII bit in
the T1 Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Pulse Density Violation Mask.
This is the mask bit for the corresponding PDVI bit in the T1
Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Loop Code Enable Detected Mask.
This is the mask bit for the corresponding LLEDI bit in the
T1 Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Loop Code Disable Detected Mask.
This is the mask bit for the corresponding LLDDI bit in
the T1 Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Bit Oriented Message Mask.
This is the mask bit for the corresponding BOMI bit in the T1
Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Bit Oriented Message Match Mask.
This is the mask bit for the corresponding BOMMI bit in
the T1 Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Signaling Interrupt Status.
This is the mask bit for the corresponding CASRI bit in the T1
Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the interrupt
bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
One Second Interrupt Status.
This is the mask bit for the corresponding ONESECI bit in the
T1 Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Two Second Interrupt Status.
This is the mask bit for the corresponding TWOSECI bit in the
T1 Receive Line and Timer Interrupt Status - R Address Y35. If this mask bit is one, the
interrupt bit will remain inactive. If this mask bit is zero, the interrupt bit will function normally.
Table 158 - T1 Receive Line and Timer Interrupt Mask - R/W Address Y45
14
D4Y48M
(0)
13
SECYM
(0)
12
ESFYM
(0)
11
T1DMYM
(0)
10
9
(0)
VEIM
(0)
8
PEIM
(0)
7
PDVM
(0)
6
LLEDM
(0)
5
LLDDM
(0)
4
BOMM
(0)
3
BOMMM
(0)
2
CASRM
(0)
1
ONESEC
M
(0)
TWOSEC
M
(0)
0
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